256K x 32
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MP4045
IDT7MP4145
FEATURES:
• High density 1 megabyte static RAM module
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module) for
IDT7MP4045 and 72 pin SIMM (Single In-line Memory
Module) for IDT7MP4145
• Very fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MP4045/4145 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MP4045 is available with
access time as fast as 10ns with minimal power consumption.
The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig-
zag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module) where as the 7MP4145 is packaged in a 72
pin SIMM (Single In-line Memory Module). The 4045 ZIP
configuration allows 64 pins to be placed on a package 3.65
inches long and 0.365 inches wide. The 7MP4045 ZIP is only
0.585 inches high, this low profile package is ideal for systems
with minimum board spacing while the SIMM configuration
allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4045/4145 are TTL-
compatible and operate from a single 5V supply. Full asyn-
chronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
Identification pins are provided for applications in which
different density versions of the module are used. In this way,
the target system can read the respective levels of PD
pins
to
determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel
covered by 30 micro-inches minimum of selective gold.
PIN CONFIGURATION – 7MP4045
(1)
1
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
ZIP,
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
WE
CS
1
CS
3
A
14
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
PD
0
– GND
PD
1
– GND
FUNCTIONAL BLOCK DIAGRAM
CS
1
CS
2
CS
3
CS
4
ADDRESS
18
2
SIMM
TOP VIEW
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS
2
CS
4
A
17
PD
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
OE
WE
OE
8
256K x 32
RAM
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
2703 drw 01
8
8
8
2703 drw 02
I/O
0-31
PIN NAMES
I/O
0
–
31
A
0
–
17
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
2703 tbl 01
CS
1–4
WE
OE
PD
0–1
V
CC
GND
NC
NOTE:
1. Pins 2 and 3 (PD
0
and PD
1
) are read by the user to determine the density
of the module. If PD
0
reads GND and PD
1
reads GND, then the module
has a 256K depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2703/7
15.2
1
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN(C)
C
IN(A)
C
I/O
Parameter
(1)
Input Capacitance
(
CS
)
Input Capacitance
(Address & Control)
I/O Capacitance
Conditions
V
(IN)
= 0V
V
(IN)
= 0V
V
(OUT)
= 0V
Max.
20
70
12
Unit
pF
pF
pF
2703 tbl 02
PIN CONFIGURATION – 7MP4145
(1)
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
NOTE:
1. This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2703 tbl 03
A
14
CS
1
CS
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
SIMM
TOP VIEW
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
PD
0
- GND
PD
1
- GND
PD
2
- OPEN
PD
3
- OPEN
NOTE:
1. V
IL
(min) = –1.5V for pulse width less than 10ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
5.0V
±
10%
2703 tbl 04
TRUTH TABLE
Mode
Standby
Read
Write
Read
CS
OE
WE
Output
High-Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Active
Active
Active
2703 tbl 05
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
NC
NC
2703 drw 15
H
L
L
L
X
L
X
H
X
H
L
H
NOTE:
1. Pins 3,4,6,and 7 (PD
0
-
3
) are read by the user to determine the density of
the module. If PD
0
, PD
1
read GND and PD
2,
PD
3
read OPEN, then the
module has a 256K depth.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Value
–0.5 to +7.0
0 to +70
–10 to +85
–55 to +125
50
Unit
V
°C
°C
°C
mA
NOTE:
2703 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
15.2
2
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±10%,
T
A
= 0°C to +70°C)
’4045SxxZ, ’4045/4145SxxM
–15
Symbol
t
RC
t
AA
t
ACS
t
CLZ(1)
t
OE
t
OLZ(1)
t
CHZ(1)
t
OHZ(1)
t
OH
t
PU(1)
t
PD(1)
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ(1)
t
DW
t
DH
t
OW(1)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Min.
15
—
—
3
—
0
—
—
3
0
—
15
12
12
0
12
0
—
10
0
0
Max.
—
15
15
—
8
—
8
8
—
—
15
—
—
—
—
—
—
8
—
—
—
Read Cycle
20
—
—
5
—
0
—
—
3
0
—
20
15
15
0
15
0
—
12
0
0
—
20
20
—
10
—
10
10
—
—
20
—
—
—
—
—
—
13
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2703 tbl 11
–20
Min.
Max.
Unit
Write Cycle
NOTE:
1. This parameter is guaranteed by design but not tested.
15.2
4
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OH
t
OLZ
t
ACS
t
CLZ (5)
(5)
t
OHZ
t
CHZ
(5)
(5)
DATA OUT
2703 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
t
OH
DATA VALID
2703 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3
(1,3,4)
CS
t
ACS
t
CLZ
DATA
OUT
(5)
t
CHZ
(5)
2703 drw 06
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected.
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
= V
IL
.
5. Transition is measured
±200mV
from steady state. This parameter is guaranteed by design, but not tested.
15.2
5
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