®
Integrated Device Technology, Inc.
128K x 8
64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE
DESCRIPTION:
IDT7M1001
IDT7M1003
FEATURES
• High-density 1M/512K CMOS Dual-Port Static RAM
module
• Fast access times:
—Commercial 35, 40ns
—Military 40, 50ns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (leadless chip carriers) compo-
nents on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL-compatible
PIN CONFIGURATION
(1)
V
CC
R/
W
L
OE
L
CS
L
SEM
L
A
0L
A
1L
GND
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
A
16L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
R/
W
R
OE
R
CS
R
SEM
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
A
16R
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
V
CC
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 high-
speed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two IDT FCT138 decoders or depopu-
lated using only four IDT7006s and two decoders.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (
SEM
) “hand-
shake” signaling. The IDT7M1001/1003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users re-
sponsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1001/1003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with di-
mensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 35ns over the commercial temperature range are
available.
All inputs and outputs of the IDT7M1001/1003 are TTL-
compatible and operate from a single 5V supply. Fully asyn-
chronous circuitry is used, requiring no clocks or refreshing for
operation of the module.
All IDT military module semiconductor components are
manufacured in compliance with the latest revision of MIL-
STD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN NAMES
Left Port
A (0–16)
L
I/O (0–7)
L
R/
W
L
CS
L
OE
L
SEM
L
Right Port
A (0–16)
R
I/O (0–7)
R
R/
W
R
CS
R
OE
R
SEM
R
Description
Address Inputs
Data Inputs/Outputs
Read/Write Enables
Chip Select
Output Enable
Semaphore Control
Power
Ground
2804 tbl 01
V
CC
GND
2804 drw 01
DIP
TOP VIEW
NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected
to GND for proper operation of the module.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
MARCH 1995
DSC-7066/5
7.5
1
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
7M1001
CS
L
L_A16
L_A15
L_A14
CS
R
CS
L
CS
R
CS
L
L_CS
74FCT138
74FCT138
R_CS
L_A0-13
L_OE
L_R/W
L_I/O0-7
CS
L
CS
R
CS
L
CS
R
CS
L
7006
7006
7006
L_SEM
7M1003
L_A15
L_A14
L_CS
74FCT138
74FCT138
R_CS
L_A0-13
L_OE
L_R/W
L_I/O0-7
CS
L
CS
R
CS
L
R
CS
CS
L
7006
7006
7006
L_SEM
7.5
7025
CS
R
CS
R
CS
R
7006
7006
7006
7006
R_I/O0-7
CS
L
CS
R
R_R/W
R_OE
R_A0-13
R_A14
R_A15
R_A16
CS
L
7006
CS
R
R_SEM
2804 drw 02
R_I/O0-7
R_R/W
R_OE
R_A0-13
R_A14
R_A15
CS
L
7006
CS
R
R_SEM
2804 drw 03
2
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2804 tbl 04
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
Commercial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2804 tbl 02
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)b
b
Typ.
5.0
0
-
-
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2804 tbl 05
CAPACITANCE
Symbol
C
IN1
C
IN2
(1)
(T
A
= +25°C, f = 1.0MHz)
Test Conditions
V
IN
= 0V
V
IN
= 0V
Max.
15
100
Unit
pF
pF
Parameter
Input Capacitance
(
CS
or
SEM
NOTE:
1. V
IL
(min.) = –3.0V for pulse width less than 20ns.
)
Input Capacitance
(Data, Address,
All Other Controls)
C
OUT
Output Capacitance
(Data)
V
OUT
= 0V
100
pF
2804 tbl 03
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= –55°C to +125°C or 0°C to +70°C)
Commercial
Symbol
I
CC2
I
CC1
I
SB1
Parameter
Dynamic Operating
Current (Both Ports Active)
Standby Supply
Current (One Port Active)
Standby Supply
Current (TTL Levels)
Full Standby Supply
Current (CMOS Levels)
Test Conditions
V
CC
= Max.,
CS
≤
V
IL
,
SEM
≥
V
IH
Outputs Open, f = f
MAX
V
CC
= Max., L_
CS
or R_
CS
≥
V
IH
Outputs Open, f = f
MAX
V
CC
= Max., L_
CS
and R_
CS
≥
V
IH
Outputs Open, f = f
MAX
L_
SEM
and R_
SEM
≥
V
CC
–0.2V
I
SB2
L_
CS
and R_
CS
≥
V
CC
–0.2V
V
IN
> V
CC
0.2V or < 0.2V
L_
SEM
and R_
SEM
≥
V
CC
–0.2V
—
125
65
—
245
125
mA
Military
Min. Max.
(1)
Max.
(2)
Min. Max.
(1)
Max.
(2)
Unit
—
—
—
940
750
565
660
470
285
—
—
—
1130
905
685
790
565
345
mA
mA
mA
NOTES:
1. IDT7M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.
2804 tbl 06
7.5
3
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0V
±
10%, T
A
= –55°C to +125°C and 0°C to +70°C)
Symbol
|I
LI
|
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage
(Address, Data & Other Controls)
Input Leakage
(
CS
and
SEM
)
Output Leakage
(Data)
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.
CS
≥
V
IH,
V
OUT
= GND to V
CC
V
CC
= Min.
V
CC
= Min.
I
OL
= 4mA
I
OH
= –4mA
IDT7M1001
Min.
Max.
—
—
—
—
2.4
80
10
80
0.4
—
IDT7M1003
Min.
Max.
—
—
—
—
2.4
40
10
40
0.4
—
Unit
µA
µA
µA
V
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
+5 V
+5 V
480
Ω
DATA
OUT
255Ω
30 pF*
DATA
OUT
255Ω
480
Ω
5 pF*
2804 drw 04
2804 drw 05
Figure 1. Output Load
Figure 2. Output Load
(for t
CLZ
, t
CHZ
, t
OLZ
. t
OHZ
, t
WHZ
, t
OW
)
*Including scope and jig.
7.5
4
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, T
A
= -55°C to +125°C and 0°C to +70°C)
–35
–40
–50
Symbol
Read Cycle
t
RC
t
AA
t
ACS(2)
t
OE
t
OH
t
CLZ(1)
t
CHZ(1)
t
OLZ(1)
t
OHZ(1)
t
PU(1)
t
PD(1)
t
SOP
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Output Hold From Address Change
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Chip Select to Power-Up Time
Chip Disable to Power-Down Time
SEM
35
—
—
—
3
3
—
3
—
0
—
15
—
35
35
20
—
—
20
—
20
—
50
—
40
—
—
—
3
3
—
3
—
0
—
15
—
40
40
25
—
—
20
—
20
—
50
—
50
—
—
—
3
3
—
3
—
0
—
15
—
50
50
30
—
—
25
—
25
—
50
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flag Update Pulse (
OE
or
SEM
)
Write Cycle
t
WC
t
CW(2)
t
AW
t
AS1(3)
t
AS2
t
WP
t
WR(4)
t
DW
t
DH(4)
t
OHZ(1)
t
WHZ(1)
t
OW(1,
4)
t
SWRD
t
SPS
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up to Write Pulse Time
Address Set-up to
CS
Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Disable to Output in High-Z
Write Enable to Output in High-Z
Output Active from End-of-Write
SEM
SEM
35
30
30
5
0
30
0
25
0
—
—
0
15
15
—
—
—
—
—
—
—
—
—
20
20
—
—
—
40
35
35
5
0
35
0
30
0
—
—
0
15
15
—
—
—
—
—
—
—
—
—
20
20
—
—
—
50
40
40
5
0
40
0
35
0
—
—
0
15
15
—
—
—
—
—
—
—
—
—
25
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flag Write to Read Time
Flag Contention Window
Port-to-Port Delay Timing
t
WDD(5)
t
DDD(5)
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
—
—
60
45
—
—
65
50
—
—
70
55
ns
ns
2804 tbl 09
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM
CS
≤
V
IL
and
SEM
≥
V
IH
. To access semaphore,
CS
≥
V
IH
and
SEM
≤
V
IL
.
3. t
AS1
= 0 if R/
W
is asserted LOW simultaneously with or after the
CS
LOW transition.
4. For
CS
controlled write cycles, t
WR
= 5ns, t
DH
= 5ns, t
OW
= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.5
5
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