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MT46H64M32LFMA-6AIT:B: 产品描述DDR DRAM,; 产品类别存储存储; 文件大小3MB，共104页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/

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MT46H64M32LFMA-6AIT:B概述

DDR DRAM,

MT46H64M32LFMA-6AIT:B规格参数

参数名称	属性值
厂商名称	Micron Technology
包装说明	,
Reach Compliance Code	compliant
内存集成电路类型	DDR DRAM
Base Number Matches	1

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Preliminary

‡

2Gb: x16, x32 Automotive Mobile LPDDR SDRAM

Features

Automotive Mobile LPDDR SDRAM

MT46H128M16LF – 32 Meg x 16 x 4 Banks

MT46H64M32LF – 16 Meg x 32 x 4 Banks

MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2

MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4

MT46H256M32R4 - 32 Meg x 16 x 4 Banks x 4

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh; 32ms for the automotive temperature

range

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-54

-6

-75

Clock Rate

200 MHz

185 MHz

166 MHz

133 MHz

Access Time

5.0ns

6.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 128 Meg x 16 (32 Meg x 16 x 4 banks)

– 64 Meg x 32 (16 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard

– Reduced page-size

– 4-die stack reduced page-size

– 2-die stack standard

– 4-die stack standard

• Plastic "green" package

– 60-ball VFBGA (10mm x 10mm)

– 90-ball VFBGA (9mm x 13mm)

• PoP (plastic "green" package)

– 168-ball VFBGA (12mm x 12mm)

– 168-ball WFBGA (12mm x 12mm)

– 240-ball WFBGA (14mm x 14mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 5.4ns @ CL = 3 (185 MHz)

– 6ns @ CL = 3 (166 MHz)

– 7.5ns @ CL = 3 (133 MHz)

• Power

– Standard I

DD2

DD6

• Product grade

– Automotive (package-level burn-in)

• Operating temperature range

– From –40˚C to +85˚C

– From –40˚C to +105˚C

• Design revision

Notes:

Mark

128M16

64M32

-5

-54

-6

-75

None

Contact factory for availability.

Available in the 168-ball JV package only.

Available only for x16 configuration.

Available only for x32 configuration.

PDF: 09005aef84e25f2e

t79m_ait_aat_mobile_lpddr.pdf - Rev. A 08/12 EN

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Preliminary

2Gb: x16, x32 Automotive Mobile LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Functional Block Diagrams ............................................................................................................................... 8

Ball Assignments ............................................................................................................................................ 10

Ball Descriptions ............................................................................................................................................ 14

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 19

Electrical Specifications .................................................................................................................................. 25

Electrical Specifications – I

Parameters ........................................................................................................ 28

Electrical Specifications – AC Operating Conditions ......................................................................................... 34

Output Drive Characteristics ........................................................................................................................... 39

Functional Description ................................................................................................................................... 42

Commands .................................................................................................................................................... 43

DESELECT ................................................................................................................................................. 44

NO OPERATION ......................................................................................................................................... 44

LOAD MODE REGISTER ............................................................................................................................. 44

ACTIVE ...................................................................................................................................................... 44

READ ......................................................................................................................................................... 45

WRITE ....................................................................................................................................................... 46

PRECHARGE .............................................................................................................................................. 47

BURST TERMINATE ................................................................................................................................... 48

AUTO REFRESH ......................................................................................................................................... 48

SELF REFRESH ........................................................................................................................................... 49

DEEP POWER-DOWN ................................................................................................................................. 49

Truth Tables ................................................................................................................................................... 50

State Diagram ................................................................................................................................................ 55

Initialization .................................................................................................................................................. 56

Standard Mode Register .................................................................................................................................. 59

Burst Length .............................................................................................................................................. 60

Burst Type .................................................................................................................................................. 60

CAS Latency ............................................................................................................................................... 61

Operating Mode ......................................................................................................................................... 62

Extended Mode Register ................................................................................................................................. 63

Temperature-Compensated Self Refresh ...................................................................................................... 63

Partial-Array Self Refresh ............................................................................................................................ 64

Output Drive Strength ................................................................................................................................ 64

Status Read Register ....................................................................................................................................... 65

Bank/Row Activation ...................................................................................................................................... 67

READ Operation ............................................................................................................................................. 68

WRITE Operation ........................................................................................................................................... 79

PRECHARGE Operation .................................................................................................................................. 91

Auto Precharge ............................................................................................................................................... 91

Concurrent Auto Precharge ......................................................................................................................... 92

AUTO REFRESH Operation ............................................................................................................................. 97

SELF REFRESH Operation ............................................................................................................................... 98

Power-Down .................................................................................................................................................. 99

Deep Power-Down .................................................................................................................................... 101

Clock Change Frequency ............................................................................................................................... 103

Revision History ............................................................................................................................................ 104

Rev. A – 08/12 ............................................................................................................................................ 104

PDF: 09005aef84e25f2e

t79m_ait_aat_mobile_lpddr.pdf - Rev. A 08/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Preliminary

2Gb: x16, x32 Automotive Mobile LPDDR SDRAM

Features

List of Figures

Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 8

Figure 3: Functional Block Diagram (x32) ......................................................................................................... 9

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 10

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 11

Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 12

Figure 7: 240-Ball FBGA – 14mm x 14mm (Top View), x32 only ........................................................................ 13

Figure 8: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 16

Figure 9: Dual Rank, Single Channel (2 Die) Package Block Diagram ................................................................ 17

Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram .............................................................. 18

Figure 11: 60-Ball FBGA (10mm x 10mm), Package Code: B7 ........................................................................... 19

Figure 12: 90-Ball FBGA (9mm x 13mm), Package Code: CX ............................................................................. 20

Figure 13: 168-Ball FBGA (12mm x 12mm), Package Code: JV .......................................................................... 21

Figure 14: 168-Ball FBGA (12mm x 12mm), Package Code: KQ ......................................................................... 22

Figure 15: 168-Ball FBGA (12mm x 12mm), Package Code: MA ........................................................................ 23

Figure 16: 240-Ball FBGA (14mm x 14mm), Package Code: MC ........................................................................ 24

Figure 17: Typical Self Refresh Current vs. Temperature .................................................................................. 33

Figure 18: ACTIVE Command ........................................................................................................................ 45

Figure 19: READ Command ........................................................................................................................... 46

Figure 20: WRITE Command ......................................................................................................................... 47

Figure 21: PRECHARGE Command ................................................................................................................ 48

Figure 22: DEEP POWER-DOWN Command ................................................................................................... 49

Figure 23: Simplified State Diagram ............................................................................................................... 55

Figure 24: Initialize and Load Mode Registers ................................................................................................. 57

Figure 25: Alternate Initialization with CKE LOW ............................................................................................ 58

Figure 26: Standard Mode Register Definition ................................................................................................. 59

Figure 27: CAS Latency .................................................................................................................................. 62

Figure 28: Extended Mode Register ................................................................................................................ 63

Figure 29: Status Read Register Timing ........................................................................................................... 65

Figure 30: Status Register Definition .............................................................................................................. 66

Figure 31: READ Burst ................................................................................................................................... 69

Figure 32: Consecutive READ Bursts .............................................................................................................. 70

Figure 33: Nonconsecutive READ Bursts ........................................................................................................ 71

Figure 34: Random Read Accesses .................................................................................................................. 72

Figure 35: Terminating a READ Burst ............................................................................................................. 73

Figure 36: READ-to-WRITE ............................................................................................................................ 74

Figure 37: READ-to-PRECHARGE .................................................................................................................. 75

Figure 38: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 76

Figure 39: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 77

Figure 40: Data Output Timing –

AC and

DQSCK .......................................................................................... 78

Figure 41: Data Input Timing ......................................................................................................................... 80

Figure 42: Write – DM Operation .................................................................................................................... 81

Figure 43: WRITE Burst ................................................................................................................................. 82

Figure 44: Consecutive WRITE-to-WRITE ....................................................................................................... 83

Figure 45: Nonconsecutive WRITE-to-WRITE ................................................................................................. 83

Figure 46: Random WRITE Cycles .................................................................................................................. 84

Figure 47: WRITE-to-READ – Uninterrupting ................................................................................................. 85

Figure 48: WRITE-to-READ – Interrupting ...................................................................................................... 86

Figure 49: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 87

Figure 50: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 88

PDF: 09005aef84e25f2e

t79m_ait_aat_mobile_lpddr.pdf - Rev. A 08/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Preliminary

2Gb: x16, x32 Automotive Mobile LPDDR SDRAM

Features

Figure 51:

Figure 52:

Figure 53:

Figure 54:

Figure 55:

Figure 56:

Figure 57:

Figure 58:

Figure 59:

Figure 60:

Figure 61:

Figure 62:

WRITE-to-PRECHARGE – Interrupting ........................................................................................... 89

WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 90

Bank Read – With Auto Precharge ................................................................................................... 93

Bank Read – Without Auto Precharge .............................................................................................. 94

Bank Write – With Auto Precharge .................................................................................................. 95

Bank Write – Without Auto Precharge ............................................................................................. 96

Auto Refresh Mode ........................................................................................................................ 97

Self Refresh Mode .......................................................................................................................... 99

Power-Down Entry (in Active or Precharge Mode) .......................................................................... 100

Power-Down Mode (Active or Precharge) ....................................................................................... 101

Deep Power-Down Mode .............................................................................................................. 102

Clock Stop Mode .......................................................................................................................... 103

PDF: 09005aef84e25f2e

t79m_ait_aat_mobile_lpddr.pdf - Rev. A 08/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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