IDT74ALVC126
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE
BUS BUFFER GATE
WITH 3-STATE OUTPUTS
FEATURES:
DESCRIPTION:
IDT74ALVC126
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
µ
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SOIC, SSOP, and TSSOP packages
This quadruple bus buffer gate is built using advanced dual metal CMOS
technology. The ALVC126 features independent line drivers with 3-state
outputs. Each output is disabled when the associated output-enable (OE) input
is low.
The ALVC126 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
3
OE
10
1
A
2
3
1
Y
3
A
9
8
3
Y
2
OE
4
4
OE
13
2
A
5
6
2
Y
4
A
12
11
4
Y
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
AUGUST 2000
DSC-4636/1
IDT74ALVC126
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
1
OE
1
A
1
Y
2
OE
2
A
2
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4
OE
4
A
T
STG
I
OUT
I
IK
I
OK
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
4
Y
3
OE
3
A
3
Y
I
CC
I
SS
GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
SOIC/ SSOP/ TSSOP
TOP VIEW
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
xA
xY
Data Inputs
3-State Outputs
Description
Output Enable Inputs
FUNCTION TABLE
(EACH BUFFER)
(1)
Inputs
xOE
H
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
Output
xA
H
L
X
xY
H
L
Z
2
IDT74ALVC126
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
10
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74ALVC126
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Gate Outputs enabled
Power Dissipation Capacitance per Gate Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
20
1
V
CC
= 3.3V ± 0.3V
Typical
28
2
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
xA to xY
Output Enable Time
xOE to xY
Output Disable Time
xOE to xY
1
5
1.7
4.4
1.7
4.2
ns
1.5
5.6
1.5
5.3
1.5
4.5
ns
Min.
1
Max.
3.5
V
CC
= 2.7V
Min.
1.1
Max.
3.1
V
CC
= 3.3V ± 0.3V
Min.
1.1
Max.
3
Unit
ns
NOTE:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
4
IDT74ALVC126
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500Ω
Pulse
Generator
(1, 2)
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
6
2.7
1.5
300
300
50
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Quad Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALVC Quad Link
V
IN
D.U.T.
R
T
V
OUT
500Ω
C
L
ALVC Quad Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
REM
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Quad Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH2
t
PHL2
ALVC Quad Link
t
SU
t
H
t
SU
t
H
Set-up, Hold, and Release Times
INPUT
t
PLH1
t
PHL1
OUTPUT 1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
V
T
ALVC Quad Link
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Pulse Width
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
