FAST CMOS
OCTAL LATCHED
TRANSCEIVER
Integrated Device Technology, Inc.
IDT54/74FCT543T/AT/CT/DT
IDT54/74FCT2543T/AT/CT
FEATURES:
• Common features:
– Low input and output leakage
≤1µA
(max.)
– CMOS power levels
– True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT543T:
– Std., A, C and D speed grades
– High drive outputs (-15mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
• Features for FCT2543T:
– Std., A, and C speed grades
– Resistor outputs (-15mA I
OH
, 12mA I
OL
Com.)
(-12mA I
OH
, 12mA I
OL
Mil.)
– Reduced system switching noise
DESCRIPTION:
The FCT543T/FCT2543T is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
This device contains two sets of eight D-type latches with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (
CEAB
) input must
be LOW in order to enter data from A
0
–A
7
or to take data from
B
0
–B
7
, as indicated in the Function Table. With
CEAB
LOW,
a LOW signal on the A-to-B Latch Enable (
LEAB
) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the
LEAB
signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With
CEAB
and
OEAB
both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA
,
LEBA
and
OEBA
inputs.
The FCT2543T has balanced output drive with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
D
LE
A
0
Q
D
LE
Q
B
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DETAIL A x 7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEBA
OEAB
CEBA
LEBA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CEAB
2613 drw 01
LEAB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
JANUARY 1995
DSC-4203/5
6.17
1
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
11
12
14
13
2613 drw 02
A
7
CEAB
GND
NC
OEAB
LEAB
B
7
LEBA
OEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
1
2
3
4
5
6
7
8
9
10
24
23
22
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
E24-1
21
20
19
18
17
16
15
Vcc
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
A
0
OEBA
LEBA
NC
Vcc
CEBA
B
0
4
3
2
1
28 27 26
25
24
23
22
21
20
5
6
7
8
9
10
PIN CONFIGURATIONS
A
1
A
2
A
3
NC
A
4
A
5
A
6
L28-1
11
19
12 13 14 15 16 17 18
B
1
B
2
B
3
NC
B
4
B
5
B
6
2613 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
2613 tbl 01
FUNCTION TABLE
(1, 2)
For A-to-B (Symmetric with B-to-A)
Inputs
Latch
Status
Output
Buffers
B
0
–B
7
High Z
—
High Z
Current A Inputs
Previous* A Inputs
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
CEAB
H
—
—
L
L
LEAB
—
H
—
L
H
OEAB
—
—
H
L
L
A-to-B
Storing
Storing
—
Transparent
Storing
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
NOTES:
2613 tbl 02
1. * Before
LEAB
LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
— = Don’t Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA
,
LEBA
and
OEBA
.
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°C
°C
°C
W
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2613 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
2613 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.17
2
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
Unit
V
V
±
1
±
1
±
1
±
1
±
1
–1.2
—
1
µ
A
µ
A
µ
A
V
mV
mA
2613 lnk 05
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR 543T/AT/CT/DT
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 48mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 64mA COM'L.
(3)
V
CC
= Max., V
O
= GND
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2.0
—
–60
—
Typ.
(2)
3.3
3.0
0.3
–120
—
Max.
—
—
0.55
–225
±1
Unit
V
V
V
mA
µA
2613 lnk 06
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
OUTPUT DRIVE CHARACTERISTICS FOR 2543T/AT/CT/DT
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OL
= 12mA
Min.
16
–16
2.4
—
Typ.
(2)
48
–48
3.3
0.3
Max.
—
—
—
0.50
Unit
mA
mA
V
V
2613 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
6.17
3
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
LEAB
)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
LEAB
)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
FCTxxxT
FCT2xxxT
Test Conditions
(1)
Min. Typ.
(2)
Max.
—
—
—
0.5
0.15
0.06
2.0
0.25
0.12
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
FCTxxxT
FCT2xxxT
—
—
—
—
—
—
—
—
1.5
0.6
2.0
1.1
3.8
1.5
6.0
3.8
3.5
2.2
5.5
4.2
7.3
(5)
4.0
(5)
16.3
(5)
13.0
(5)
mA
V
IN
= 3.4V
V
IN
= GND
FCTxxxT
FCT2xxxT
V
IN
= V
CC
V
IN
= GND
FCTxxxT
FCT2xxxT
V
IN
= 3.4V
V
IN
= GND
FCTxxxT
FCT2xxxT
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2613 tbl 08
6.17
4
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT543T/
FCT2543T
Com'l.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Parameter
Propagation Delay
Transparant Mode
An to Bn or Bn to An
Propagation Delay
LEBA
to An,
LEAB
to Bn
Output Enable Time
OEBA
or
OEAB
to An or Bn
CEBA
or
CEAB
to An or Bn
Output Disable Time
OEBA
or
OEAB
to An or Bn
CEBA
or
CEAB
to An or Bn
Set-up Time, HIGH or LOW
An or Bn to
LEBA
or
LEAB
Hold Time, HIGH or LOW
An or Bn to
LEBA
or
LEAB
LEBA
or
LEAB
Pulse Width
LOW
Condition
(1)
C
L
= 50pF
R
L
= 500
Ω
Min
.
(2)
1.5
Max.
8.5
Mil.
Min
.
(2)
1.5
Max.
10.0
Min
.
(2)
1.5
FCT543AT/
FCT2543AT
Com'l.
Max.
6.5
Mil.
Min
.
(2)
1.5
Max.
7.5
Unit
ns
1.5
1.5
12.5
12.0
1.5
1.5
14.0
14.0
1.5
1.5
8.0
9.0
1.5
1.5
9.0
10.0
ns
ns
1.5
9.0
1.5
13.0
1.5
7.5
1.5
8.5
ns
3.0
2.0
5.0
—
—
—
3.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
ns
ns
ns
2513 tbl 09
FCT543CT/
FCT2543CT
Com'l.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Parameter
Propagation Delay
Transparant Mode
An to Bn or Bn to An
Propagation Delay
LEBA
to An,
LEAB
to Bn
Output Enable Time
OEBA
or
OEAB
to An or Bn
CEBA
or
CEAB
to An or Bn
Output Disable Time
OEBA
or
OEAB
to An or Bn
CEBA
or
CEAB
to An or Bn
Set-up Time, HIGH or LOW
An or Bn to
LEBA
or
LEAB
Hold Time, HIGH or LOW
An or Bn to
LEBA
or
LEAB
LEBA
or
LEAB
Pulse Width
LOW
Condition
(1)
C
L
= 50pF
R
L
= 500
Ω
Min
.
(2)
1.5
Max.
5.3
Mil.
Min
.
(2)
1.5
Max.
6.1
Min
.
(2)
1.5
FCT543DT
Com'l.
Max.
4.4
Mil.
Min
.
(2)
—
Max.
—
Unit
ns
1.5
1.5
7.0
8.0
1.5
1.5
8.0
9.0
1.5
1.5
5.0
5.4
—
—
—
—
ns
ns
1.5
6.5
1.5
7.5
1.5
4.3
—
—
ns
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
1.5
1.5
3.0
(3)
—
—
—
—
—
—
—
—
—
ns
ns
ns
2513 tbl 10
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
6.17
5
FPGA/CPLD
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