®
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
DESCRIPTION:
IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
IDT54/74FCT543 equivalent to FAST™ speed
IDT54/74FCT543A 25% faster than FAST
IDT54/74FCT543C 40% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
I
OL
= 64mA (commercial), 48mA (military)
Separate controls for data flow in each direction
Back-to-back latches for storage
CMOS power levels (1mW typ. static)
Substantially lower input current levels than FAST
(5µA max.)
TTL input and output level compatible
CMOS output level compatible
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT543/A/C is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
These devices contain two sets of eight D-type latches with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (
CEAB
) input must
be LOW in order to enter data from A
0
–A
7
or to take data from
B
0
–B
7
, as indicated in the Function Table. With
CEAB
LOW,
a LOW signal on the A-to-B Latch Enable (
LEAB
) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the
LEAB
signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With
CEAB
and
OEAB
both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA
,
LEBA
and
OEBA
inputs.
FUNCTIONAL BLOCK DIAGRAMS
DETAIL A
D
LE
A
0
Q
D
LE
Q
B
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DETAIL A x 7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
2614 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4602/3
7.17
1
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT861 10-BIT TRANSCEIVERS
LEBA
OEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
INDEX
P24-1,
D24-1,
SO24-2
&
E24-1
21
20
19
18
17
16
15
14
13
A
7
CEAB
GND
NC
OEAB
LEAB
B
7
LCC
TOP VIEW
Vcc
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
A
0
OEBA
LEBA
NC
Vcc
CEBA
B
0
4
3
2
1
28 27 26
25
24
23
5
6
7
8
9
10
A
1
A
2
A
3
NC
A
4
A
5
A
6
L28-1
22
21
20
11
19
12 13 14 15 16 17 18
B
1
B
2
B
3
NC
B
4
B
5
B
6
2614 drw 02
DIP/SOIC/CERPACK
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
2614 tbl 02
FUNCTION TABLE
(1,2)
For A-to-B (Symmetric with B-to-A)
Inputs
Latch
Status
Output
Buffers
B
0
–B
7
High Z
—
High Z
Current A Inputs
Previous* A Inputs
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
CEAB
H
—
—
L
L
LEAB
—
H
—
L
H
OEAB
—
—
H
L
L
A-to-B
Storing
Storing
—
Transparent
Storing
LOGIC SYMBOL
NOTES:
2614 tbl 01
1. * Before
LEAB
LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
— = Don’t Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA
,
LEBA
and
OEBA
.
LEAB CEAB CEBA LEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEAB
2614 drw 03
7.17
2
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
(2)
V
TERM
Terminal Voltage
with Respect
to GND
(3)
V
TERM
Terminal Voltage
with Respect
to GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
I
OUT
DC Output Current
Commercial
Military
Unit
–0.5 to +7.0 –0.5 to +7.0
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions Typ.
V
IN
= 0V
V
OUT
= 0V
6
8
Max.
10
12
Unit
pF
pF
–0.5 to V
CC
–0.5 to V
CC
V
NOTE:
2614 tbl 04
1. This parameter is guaranteed by characterization data and not tested.
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
NOTES:
2614 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Inputs and V
CC
terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V, V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O pins)
Input LOW Current
(Except I/O pins)
Input HIGH Current
(I/O pins Only)
Input LOW Current
(I/O pins Only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300µA
I
OH
= –12mA MIL.
I
OH
= –15mA COM’L.
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300µA
I
OL
= 48mA MIL.
(5)
I
OL
= 64mA COM’L.
(5)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC(4)
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
Unit
V
V
µA
µA
µA
µA
V
mA
V
–5
(4)
–5
15
15
(4)
–15
(4)
–15
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.55
0.55
V
NOTES:
2614 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum I
OL
values per output, for 8 outputs turned on simultaneously. Total maximum I
OL
(all outputs) is 512mA for commercial and 384mA
for military. Derate I
OL
for number of outputs exceeding 8 turned on simultaneously.
7.17
3
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power
Supply Current
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max., V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
LEAB
)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (
LEAB
)
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
Eight Bits Toggling
at f
i
= 5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
1.7
4.0
mA
V
IN
= 3.4V
V
IN
= GND
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
2.2
6.0
—
7.0
12.8
(5)
V
IN
= 3.4V
V
IN
= GND
—
9.2
21.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2614 tbl 06
7.17
4
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT543
Com’l.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Parameter
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA
to A
n
,
LEAB
to B
n
Output Enable Time
OEBA
or
OEAB
to A
n
or B
n
CEBA
or
CEAB
to A
n
or B
n
Output Disable Time
OEBA
or
OEAB
to A
n
or B
n
CEBA
or
CEAB
to A
n
or B
n
Set-up Time, HIGH or LOW
A
n
or B
n
to
LEBA
or
LEAB
Hold Time, HIGH or LOW
A
n
or B
n
to
LEBA
or
LEAB
Mil.
IDT54/74FCT543A
Com’l.
Mil.
IDT54/74FCT543C
Com’l.
Mil.
Condition
(1)
Min.
(2)
Max
.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
C
L
= 50pF
2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns
R
L
= 500Ω
2.5
2.0
12.5 2.5
12.0 2.0
14.0 2.5
14.0 2.0
8.0
9.0
2.5
2.0
9.0
10.0
2.5
2.0
7.0
8.0
2.5
2.0
8.0
9.0
ns
ns
2.0
9.0
2.0
13.0 2.0
7.5
2.0
8.5
2.0
6.5
2.0
7.5
ns
3.0
2.0
5.0
—
—
—
3.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
ns
ns
ns
LEBA
or
LEAB
LOW
Pulse Width
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2513 tbl 07
7.17
5
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