Integrated
Circuit
Systems, Inc.
ICS951901
Programmable Frequency Generator & Integrated Buffers for Pentium
III
Processor
Recommended Application:
Single chip clock solution for IA platform.
Output Features:
•
3 - CPU @ 2.5V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
2 - AGP @ 3.3V
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
•
2 - REF @3.3V, 14.318MHz.
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable SDRAM and CPU skew.
•
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
Skew Specifications:
•
CPU - CPU: < 175ps
•
SDRAM - SDRAM < 250ps (except SDRAM12)
•
PCI - PCI: < 500ps
•
CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
*
(AGPSEL)REF0
1
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1
These are double strength.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
Bit2
FS3
Bit7
FS2
Bit6
FS1
Bit5
FS0
Bit4
CPU
MHz
SDRAM
MHz
PCI
MHz
AGP1
SEL=1
AGP0
SEL=0
2
REF(1:0)
CPU
DIVDER
Stop
3
CPUCLK (2:0)
SDRAM
DIVDER
Stop
13
SDRAM (12:0)
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
PCI
DIVDER
Stop
5
PCICLK (4:0)
PCICLK_F
AGP
DIVDER
Config.
Reg.
2
AGP (1:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
66.67
66.67
75.00
83.31
90.00
95.00
100.00
100.00
100.00
105.00
112.00
117.99
124.09
133.34
133.34
ICS951901
66.67
100.00
133.34
75.00
83.31
90.00
95.00
66.67
100.00
133.34
105.00
112.00
117.99
124.09
100.00
133.34
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
0670B—07/15/04
ICS951901
General Description
The
ICS951901
is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
The
ICS951901
belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
MODE Pin Power Management Control Input
M ODE
Pin 21
0
1
Pin 27
SDRAM11
CPU_STOP#
Pin 28
SDRAM10
PCI_STOP#
Pin 30
SDRAM9
SDRAM_STOP#
Pin 31
SDRAM8
PD#
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16,
20
PIN NAME
VDD
AGPSEL
REF0
FS3
REF1
GND
X1
X2
FS1
PCICLK_F
FS2
PCICLK0
PCICLK (4:1)
AGP (1:0)
FS0
48MHz
MODE
24_48MHz
23
24
27
SDATA
SCLK
CPU_STOP#
SDRAM11
28
PCI_STOP#
SDRAM10
SDRAM9
30
SDRAM_STOP#
PD#
SDRAM8
26 33, 34, 36,
37, 38, 40, 41,
42
45, 46, 47
48
0670B—07/15/04
TYPE
PWR
IN
OUT
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
PWR
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48MHz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
Clock output for super I/O/USB default is 24MHz
Data pin for I
2
C circuitry 5V tolerant
Clock pin of I
2
C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode
SDRAM clock output
Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
SDRAM clock output
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms
SDRAM clock output
SDRAM clock outputs
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
21
31
SDRAM (12,
7:0)
CPUCLK (2:0)
VDDL
2
ICS951901
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
FS3
Bit7
FS2
Bit6
FS1
Bit5
FS0
Bit4
CPU
MHz
Description
SDRAM
PCI
MHz
MHz
AGP1
SEL=1
AGP0
SEL=0
Spread %
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
0.35%
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
center spread
0
1
0
PWD
Bit
Bit2
Bit 2
Bit 7:4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
66.67
66.67
75.00
83.31
90.00
95.00
100.00
100.00
100.00
105.00
112.00
117.99
124.09
133.34
133.34
75.00
75.00
75.00
83.31
83.32
90.00
90.00
95.00
95.00
105.00
105.00
112.00
117.99
124.09
129.99
140.00
66.67
100.00
133.34
75.00
83.31
90.00
95.00
66.67
100.00
133.34
105.00
112.00
117.99
124.09
100.00
133.34
100.00
112.50
150.00
111.07
166.65
60.00
120.00
63.33
126.66
70.00
140.00
84.00
88.49
93.07
97.49
105.00
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
37.50
32.14
32.14
33.32
31.25
30.00
30.00
31.67
31.67
35.00
35.00
33.60
35.40
31.02
32.50
35.00
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
75.00
64.29
64.29
66.64
62.49
60.00
60.00
63.33
63.33
70.00
70.00
67.20
70.80
62.05
64.99
70.00
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
00000
Note1
Bit 3
Bit 1
Bit 0
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit, 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note:
PWD = Power-Up Default
0670B—07/15/04
I
2
C is a trademark of Philips Corporation
3
ICS951901
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
47
46
45
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
R e s e r ve d
R e s e r ve d
R e s e r ve d
CPUCLK0
CPUCLK1
CPUCLK2
R e s e r ve d
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
13
12
11
10
9
8
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
33
34
36
37
38
40
41
42
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
BIT PIN# PWD
Bit 7
-
1
Bit 6
21
1
Bit 5
20
1
Bit 4
26
1
Bit 3
27
1
Bit 2
28
1
Bit 1
30
1
Bit 0
31
1
DESCRIPTION
R e s e r ve d
24_48MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
-
X
Bit 6
-
X
Bit 5
-
X
Bit 4
-
X
Bit 3
3
1
Bit 2
2
1
Bit 1
17
1
Bit 0
16
1
Notes:
DESCRIPTION
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF0
REF1
AGPCLK1
AGPCLK0
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0670B—07/15/04
4
ICS951901
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
2,3
45
-
-
-
-
-
-
PWD
DESCRIPTION
0
REF strength 0=1X, 1=2X
CPUCLK2 - Stop - Control
0
0 = C P U _ S TO P # w i l l c o n t r o l C P U C L K 2 ,
1=CPUCLK2 is free running even if CPU_STOP# is low
X
AGPSEL (Readback)
X
MODE (Readback)
X
C P U _ S TO P # ( R e a d b a c k )
X
P C I _ S TO P # ( R e a d b a c k )
X
S D R A M _ S TO P # ( R e a d b a c k )
AGP Speed Toggle
0
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
-
0
Bit 6
-
0
Bit 5
-
1
Bit 4
-
0
Bit 3
-
1
Bit 2
-
0
Bit 1
-
0
Bit 0
-
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT PIN# PWD
Bit 7
-
0
Bit 6
-
0
Bit 5
-
0
Bit 4
-
0
Bit 3
-
0
Bit 2
-
1
Bit 1
-
0
Bit 0
-
0
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 9: Watchdog Timer Count Register
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
1
0
0
0
0
Description
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
0670B—07/15/04
5
FPGA/CPLD
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