FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
Integrated Device Technology, Inc.
IDT54/74FCT377T/AT/CT/DT
FEATURES:
•
•
•
•
Std., A, C and D speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “live insertion”
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (
CE
) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The
CE
input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D Q
CP
CP
O
0
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4200/3
6.14
1
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
P20-1
D20-1
SO20-2
SO20-8
&
E20-1
18
17
16
15
14
13
12
11
O
3
GND
CP
O
4
D
4
LCC
TOP VIEW
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
2630 drw 02
D
0
O
0
CE
Vcc
O
7
3
2
4
5
6
7
8
PIN CONFIGURATIONS
D
1
O
1
O
2
D
2
D
3
L20-2
20 19
18
1
17
16
15
14
9 10 11 12 13
D
7
D
6
O
6
O
5
D
5
2630 drw 03
DIP/SOIC/QSOP/CERPACK
TOP VIEW
PIN DESCRIPTION
Pin Names
D
0
– D
7
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
2630 tbl 01
FUNCTION TABLE
(1)
Description
Operating Mode
Load “1”
Load “0”
Hold
CP
↑
↑
↑
H
Inputs
Outputs
D
h
l
X
X
O
H
L
No Change
No Change
CE
O
0
– O
7
CP
CE
l
l
h
H
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
NOTE:
2630 tbl 02
1. H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
Clock Transition
L = LOW Voltage Level
l = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
X = Don't Care
↑
= LOW-to-HIGH Clock Transition
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
°C
°C
°C
W
mA
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2630 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
2630 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.14
2
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL.
I
OH
= –8mA COM’L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM’L.
V
OL
I
OFF
V
H
I
CC
Output LOW Voltage
Input/Output Power Off
Leakage
(5)
Input Hysteresis
Quiescent Power
Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
2630 tbl 05
Min.
2.0
—
—
—
—
—
–60
2.4
2.0
—
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
—
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
±1
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
V
µA
mV
mA
V
I
= 2.7V
V
I
= 0.5V
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
I
OL
= 32mA MIL.
I
OL
= 48mA COM’L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= -55°C.
5. This parameter is guaranted but not tested.
6.14
3
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
CE
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz, 50% Duty Cycle
Eight Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
1.5
2.0
3.5
5.5
mA
CE
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
3.8
6.0
7.3
(5)
16.3
(5)
CE
= GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2639 tbl 05
6.14
4
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT377T
Com'l.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Mil.
Min.
(2)
Max.
FCT54/74FCT377AT
Com'l.
Min.
(2)
Max.
Mil.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
t
SU
t
H
t
SU
t
H
t
W
Propagation Delay
CP to On
Set-Up Time HIGH or LOW
Dn to CP
Hold Time HIGH or LOW
Dn to CP
Set-Up Time HIGH or LOW
CE
to CP
Hold Time HIGH or LOW
CE
to CP
Clock Pulse Width,
HIGH or LOW
C
L
= 50pF
R
L
= 500Ω
2.0
2.5
2.0
4.0
1.5
7.0
13.0
—
—
—
—
—
2.0
3.0
2.5
4.0
1.5
7.0
15.0
—
—
—
—
—
2.0
2.0
1.5
3.5
1.5
6.0
7.2
—
—
—
—
—
2.0
2.0
1.5
3.5
1.5
7.0
8.3
—
—
—
—
—
ns
ns
ns
ns
ns
ns
2630 tbl 06
IDT54/74FCT377CT
Com'l.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Mil.
Min.
(2)
Max.
FCT54/74FCT377DT
Com'l.
Min.
(2)
Max.
Mil.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
t
SU
t
H
t
SU
t
H
t
W
Propagation Delay
CP to On
Set-Up Time HIGH or LOW
Dn to CP
Hold Time HIGH or LOW
Dn to CP
Set-Up Time HIGH or LOW
CE
to CP
Hold Time HIGH or LOW
CE
to CP
Clock Pulse Width,
HIGH or LOW
C
L
= 50pF
R
L
= 500Ω
2.0
2.0
1.5
3.5
1.5
6.0
5.2
—
—
—
—
—
2.0
2.0
1.5
3.5
1.5
7.0
5.5
—
—
—
—
—
2.0
2.0
1.0
3.0
0.0
3.0
4.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2630 tbl 07
6.14
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
