1346
PRELIMINARY
CY7C1346
64K x 36 Synchronous-Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentium® and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined oper-
ation
• 64K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
•
•
•
•
•
•
— 5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel® Pen-
tium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
The CY7C1346 I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V tolerant when V
DDQ
=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1346 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the processor address strobe
(ADSP) or the controller address strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
[3:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. In order to provide proper data
during depth expansion, OE is masked during the first clock of
a read cycle when emerging from a deselected state.
Functional Description
The CY7C1346 is 3.3V 64K by 36 synchronous-pipelined
cache SRAM designed to support zero-wait-state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[15:0]
GW
BWE
BW
3
BW
2
BW
1
BW
0
CE
1
CE
2
CE
3
MODE
(A
[1;0]
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
14
16
16
14
D DQ[31:24], DP[3] Q
BYTEWRITE
REGISTERS
DQ[23:16], DP[2] Q
D
BYTEWRITE
REGISTERS
D DQ[15:8], DP[1] Q
BYTEWRITE
REGISTERS
D DQ[7:0], DP[0] Q
BYTEWRITE
REGISTERS
D
ENABLE CE
REGISTER
Q
64K X 36
MEMORY
ARRAY
36
36
D ENABLE DELAY Q
REGISTER
OE
ZZ
SLEEP
CONTROL
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ
[31:0]
DP
[3:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
February 17, 1999
PRELIMINARY
Pin Configuration
CY7C1346
BYTE2
BYTE3
DP
2
DQ
16
DQ
17
V
DDQ
V
SSQ
DQ
18
DQ
19
DQ
20
DQ
21
V
SSQ
V
DDQ
DQ
22
DQ
23
NC
V
DD
NC
V
SS
DQ
24
DQ
25
V
DDQ
V
SSQ
DQ
26
DQ
27
DQ
28
DQ
29
V
SSQ
V
DDQ
DQ
30
DQ
31
DP
3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE
1
CE
2
BW
3
BW
2
BW
1
BW
0
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DP
1
DQ
15
DQ
14
V
DDQ
V
SSQ
DQ
13
DQ
12
DQ
11
DQ
10
V
SSQ
V
DDQ
DQ
9
DQ
8
V
SS
NC
V
DD
ZZ
DQ
7
DQ
6
V
DDQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
DDQ
DQ
1
DQ
0
DP
0
BYTE1
BYTE0
Selection Guide
7C1346-166
7C1346L-166
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
L
Maximum CMOS Standby Current (mA)
Commercial
3.5
420
378
10
7C1346-133
7C1346L-133
4.0
375
340
10
7C1346-100
7C1346L-100
5.5
325
293
10
MODE
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
2
PRELIMINARY
Pin Definitions
Pin Number
Name
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Description
49–44, 81, 82, A
[15:0]
99, 100, 32–37
96–93
88
BW
[3:0]
GW
CY7C1346
Address Inputs used to select one of the 64K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[3:0]
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if
CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of
a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-
matically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When assert-
ed LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When assert-
ed LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[15:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
and DP
[3:0]
are placed in
a three-state condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power
supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects burst order. When tied to GND selects linear burst sequence. When tied
to V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
No Connects.
87
89
98
BWE
CLK
CE
1
97
92
86
CE
2
CE
3
OE
83
84
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
85
ADSC
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
64
30–28, 25–22,
19, 18,13,12,
9–6, 3–1,
80–78, 75–72,
69, 68, 63, 62
59–56, 53–51
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
31
ZZ
DQ
[31:0]
DP
[3:0]
V
DD
V
SS
V
DDQ
V
SSQ
MODE
Power Supply
Ground
I/O Power
Supply
I/O Ground
Input-
Static
-
14, 16, 38, 39,
42, 43, 50, 66
NC
3
PRELIMINARY
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz
device).
The CY7C1346 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order is user selectable, and is de-
termined by sampling the MODE input. Accesses can be initi-
ated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[3:0]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. ADSP is ignored if CE
1
is
HIGH.
CY7C1346
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[3:0]
signals. The CY7C1346 provides byte write capability
that is described in the Write Cycle Descriptions table. Assert-
ing the Byte Write Enable input (BWE) with the selected Byte
Write (BW
[3:0]
) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1346 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
[31:0]
and DP
[3:0]
inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
[31:0]
and DP
[3:0]
are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
[3:0]
) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
[15:0]
is loaded into the address register and the address ad-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ
[31:0]
and DP
[3:0]
is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1346 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
[31:0]
and DP
[3:0]
inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
[31:0]
and DP
[3:0]
are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs (A
[15:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Burst Sequences
The CY7C1346 provides a two-bit wraparound counter, fed by
A
[1:0]
, that implements either an interleaved or linear burst se-
quence. The interleaved burst sequence is designed specifi-
cally to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[15:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[3:0]
) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
[31:0]
and DP
[3:0]
inputs is written into
Interleaved Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
4
PRELIMINARY
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
CY7C1346
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
,
CE
1
, CE
2
, CE
3,
ADSP and ADSC must remain inactive for the
duration of t
ZZREC
after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
2t
CYC
Min
Max
3
2t
CYC
mA
ns
ns
Unit
5
FPGA/CPLD
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