AEC-Q100 with extended temperature range (-55°C to 125°C)
Frequencies between 115.2 MHz and 137 MHz accurate to
6 decimal points
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 ppm
Industry best G-sensitivity of 0.1 PPB/G
Low power consumption of 3.8 mA typical at 1.8V
LVCMOS/LVTTL compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5,
5.0 x 3.2, 7.0 x 5.0 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Automotive, extreme temperature and other high-rel
electronics
Infotainment systems, collision detection devices, and
in-vehicle networking
Powertrain control
Electrical Characteristics
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
115.20
-20
-25
-30
-50
Operating Temperature
Range (ambient)
T_use
-40
-40
-40
-55
Supply Voltage
Current Consumption
Vdd
Idd
1.62
2.25
–
–
Duty Cycle
Rise/Fall Time
Output High Voltage
DC
Tr, Tf
VOH
45
–
–
90%
Typ.
–
–
–
–
–
–
–
–
–
Max.
Unit
Condition
Frequency Range
137
MHz
Refer to
Tables 13 to 15
for the exact list of supported frequencies
Frequency Stability and Aging
st
Inclusive of Initial tolerance at 25°C, 1 year aging at 25°C, and
+20
ppm
variations over operating temperature, rated power supply voltage
+25
ppm
and load (15 pF ± 10%).
+30
ppm
+50
ppm
Operating Temperature Range
+85
°C
AEC-Q100 Grade 3
+105
+125
+125
°C
°C
°C
AEC-Q100 Grade 2
AEC-Q100 Grade 1
Extended cold, AEC-Q100 Grade1
Supply Voltage and Current Consumption
All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V and 3.3V
1.8
1.98
V
are supported. Contact
SiTime
for 1.5V support
–
3.63
V
6
4.9
–
1.5
1.5
–
8
6
mA
mA
No load condition, f = 125 MHz, Vdd = 2.25V to 3.63V
No load condition, f = 125 MHz, Vdd = 1.62V to 1.98V
LVCMOS Output Characteristics
55
%
3
2.5
–
ns
ns
Vdd
Vdd = 2.25V - 3.63V, 20% - 80%
Vdd = 1.8V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Output Low Voltage
VOL
–
–
10%
Vdd
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
Startup Time
Enable/Disable Time
Standby Current
VIH
VIL
Z_in
T_start
T_oe
I_std
70%
–
–
–
–
–
–
–
–
–
100
–
–
2.6
1.4
0.6
Input Characteristics
–
Vdd
Pin 1, OE
30%
–
Vdd
k
Pin 1, OE
Pin 1, OE logic high or logic low
Startup and Resume Timing
5
ms
Measured from the time Vdd reaches its rated minimum value
130
–
–
–
ns
A
A
A
f = 115.20 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Vdd = 2.8V to 3.3V,
ST
= Low, Output is weakly pulled down
Vdd = 2.5V,
ST
= Low, Output is weakly pulled down
Vdd = 1.8V,
ST
= Low, Output is weakly pulled down
Rev 1.6
July 18, 2018
www.sitime.com
SiT8925B
High Frequency, Automotive AEC-Q100 Oscillator
Table 1. Electrical Characteristics (continued)
Parameter
RMS Period Jitter
Peak-to-peak Period Jitter
RMS Phase Jitter (random)
Symbol
T_jitt
T_pk
T_phj
Min.
–
–
–
–
–
–
Typ.
1.6
1.8
12
14
0.7
1.5
Max.
2.5
3
20
30
–
–
Unit
Jitter
ps
ps
ps
ps
ps
ps
f = 125 MHz, 2.25V to 3.63V
f = 125 MHz, 1.8V
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 125 MHz, Vdd = 1.8V
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Condition
Table 2. Pin Description
Pin
Symbol
Output Enable
1
OE/NC
No Connect
2
3
4
GND
OUT
VDD
Power
Output
Power
Functionality
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
Any voltage between 0 and Vdd or Open : Specified frequen-
cy output. Pin 1 has no function.
Electrical ground
Oscillator output
Power supply voltage
[2]
[2]
[1]
[1]
Top View
OE/NC
1
4
VDD
GND
2
3
OUT
Figure 1. Pin Assignments
Notes:
1. In OE mode, a pull-up resistor of 10k or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev 1.6
Page 2 of 18
www.sitime.com
SiT8925B
High Frequency, Automotive AEC-Q100 Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance
of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[4]
Package
7050
5032
3225
2520
2016
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
JA, 4 Layer Board
(°C/W)
142
97
109
117
152
JA, 2 Layer Board
(°C/W)
273
199
212
222
252
JC, Bottom
(°C/W)
30
24
27
26
36
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
85°C
105°C
125°C
Maximum Operating Junction Temperature
93°C
113°C
133°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev 1.6
Page 3 of 18
www.sitime.com
SiT8925B
High Frequency, Automotive AEC-Q100 Oscillator
Test Circuit and Waveform
Vdd
Vout
Test
Point
tr
80% Vdd
tf
4
Power
Supply
0.1µF
3
15pF
(including probe
and fixture
capacitance)
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
1
2
Vdd
OE/NC Function
1k
Figure 2. Test Circuit
[6]
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Waveform
Timing Diagrams
90% Vdd
Vdd
50% Vdd
T_oe
Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
OE Voltage
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)
[7]
Figure 5. OE Enable Timing (OE Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
7. SiT8925 has “no runt” pulses and “no glitch” output during startup or resume.
FPGA/CPLD
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