CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
FEATURES:
•
•
•
•
•
IDT7200L
IDT7201LA
IDT7202LA
•
•
•
•
•
•
•
•
•
•
•
•
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin and functionally compatible with 720X family
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
Industrial temperature range (–40
o
C to +85
o
C) is available
(plastic packages only)
Green parts available, see ordering information
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data
on a first-in/first-out basis. The devices use Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and
simultaneous read/writes in multiprocessing and rate buffer applications.
Military grade product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
-D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0
-Q
8
)
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
XO/HF
2679 drw 01
©2006
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
1
APRIL 2006
DSC-2679/11
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
D
3
D
8
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
2679 drw 02a
4 3 2 1 32 31 30
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
Q
8
GND
NC
R
D
5
INDEX
W
NC
V
CC
D
4
PIN CONFIGURATIONS
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
3
Q
4
Q
5
2679 drw 02b
Package Type
PLASTIC DIP
PLASTIC THIN DIP
CERDIP
(1)
THIN CERDIP
SOIC
(1)
Reference
Identifier
P28-1
P28-2
D28-1
D28-3
SO28-3
TOP VIEW
Order
Code
P
TP
D
TD
SO
Package Type
LCC
(1)
PLCC
Reference
Identifier
L32- 1
J32-1
TOP VIEW
Order
Code
L
J
NOTE:
1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200.
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Storage
Temperature
DC Output
Current
Com’l & Ind'l
–0.5 to +7.0
Mil.
–0.5 to +7.0
Unit
V
Symbol
Parameter
V
CC
Supply Voltage
Commercial/Industrial/Military
GND
Supply Voltage
(1)
V
IH
Input High Voltage Com'l/Ind'l
(1)
V
IH
Input High Voltage Military
(2)
V
IL
Input Low Voltage
Commercial/Industrial/Military
T
A
Operating Temperature Commercial
T
A
Operating Temperature Industrial
T
A
Operating Temperature Military
Min.
4.5
0
2.0
2.2
—
0
–40
–55
Typ.
5.0
0
—
—
—
—
—
—
Max. Unit
5.5
V
0
—
—
0.8
70
85
125
V
V
V
V
°C
°C
°C
T
STG
I
OUT
–55 to +125
–50 to +50
–65 to +155
–50 to +50
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. For
RT/RS/XI
input, V
IH
= 2.6V (commercial).
For
RT/RS/XI
input, V
IH
= 2.8V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
2
APRIL 3, 2006
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0
o
C to +70
o
C; Industrial: V
CC
= 5V ± 10%, T
A
= –40
o
C to +85
o
C; Military: V
CC
= 5V ± 10%, T
A
= –55
o
C to +125
o
C)
IDT7200L
IDT7201LA
IDT7202LA
Com'l & Ind'l
(1)
t
A
= 12, 15, 20, 25, 35, 50 ns
Min.
Max.
–1
–10
2.4
—
—
—
1
10
—
0.4
80
5
IDT7200L
IDT7201LA
IDT7202LA
Military
(2)
t
A
= 20, 30, 50, 80 ns
Min.
Max.
–10
–10
2.4
—
—
—
10
10
—
0.4
100
15
Symbol
I
LI(3)
I
LO(4)
V
OH
V
OL
I
CC1(5,6,7)
I
CC2(5,8)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OH
= –2mA
Output Logic “0” Voltage I
OL
= 8mA
Active Power Supply Current
Standby Current (R=W=RS=FL/RT=V
IH
)
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for the 15ns and 25 ns speed grades are available as a standard device.
2. Military speed grades of 50ns and 80ns are only available for the IDT7201LA.
3. Measurements with 0.4
≤
V
IN
≤
V
CC
.
4.
R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
5. Tested with outputs open (I
OUT
= 0).
6. Tested at f = 20 MHz.
7. Typical I
CC1
= 15 + 2*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 5V, T
A
= 25
°
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive
load (in pF).
8. All Inputs = V
CC
- 0.2V or GND + 0.2V.
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
NOTE:
1. Characterized values, not currently tested.
5V
1.1K
TO
OUTPUT
PIN
680Ω
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
30pF*
2679 drw 03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
3
APRIL 3, 2006
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C; Military: V
CC
= 5V ± 10%, T
A
= –55°C to +125°C)
Commercial
IDT7200L12
IDT7201LA12
IDT7202LA12
Min.
Max.
—
20
—
8
12
3
5
5
—
20
(3)
(4,5)
Symbol
t
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RTR
t
EFL
t
HFH,FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameter
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(3)
Read Pulse Low to Data Bus at Low Z
(4)
Write Pulse High to Data Bus at Low Z
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z
(4)
Write Cycle Time
Write Pulse Width
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Set-up Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Retransmit Set-up Time
(4)
Com'l & Ind'l
(2)
IDT7200L15
IDT7201LA15
IDT7202LA15
Min.
Max.
—
25
—
10
15
3
5
5
—
25
15
10
11
0
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
40
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
Com'l & Mil.
IDT7200L20
IDT7201LA20
IDT7202LA20
Min.
Max.
—
30
—
10
20
3
5
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
Com'l & Ind'l
(2)
IDT7200L25
IDT7201LA25
IDT7202LA25
Min.
Max.
—
35
—
10
25
3
5
5
—
35
25
10
15
0
35
25
25
10
35
25
25
10
—
—
—
—
—
25
—
—
—
—
25
—
—
25
10
10
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
35
35
35
25
25
—
25
25
35
35
—
25
25
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
—
12
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
12
17
20
12
14
—
12
14
17
17
—
12
12
—
—
—
12
8
9
0
20
12
12
8
20
12
12
8
—
—
—
—
—
12
—
—
—
—
12
—
—
12
8
8
Write Recovery Time
Retransmit Recovery Time
Reset to Empty Flag Low
Reset to Half-Full and Full Flag High
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after
EF
High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after
FF
High
Read/Write to
XO
Low
Read/Write to
XO
High
XI
Pulse Width
(3)
XI
Recovery Time
XI
Set-up Time
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode
4
APRIL 3, 2006
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C; Military: V
CC
= 5V ± 10%, T
A
= –55°C to +125°C)
Military
IDT7200L30
IDT7201LA30
IDT7202LA30
Min.
Max.
—
40
—
10
30
(4)
(3)
Symbol
t
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RTR
t
EFL
t
HFH,FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Shift Frequency
Parameter
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read Pulse Low to Data Bus at Low Z
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z
(4)
Write Cycle Time
Write Pulse Width
(3)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Set-up Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Retransmit Set-up Time
(4)
Retransmit Recovery Time
Reset to Empty Flag Low
Reset to Half-Full and Full Flag High
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after
EF
High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after
FF
High
Read/Write to
XO
Low
Read/Write to
XO
High
XI
Pulse Width
(3)
XI
Recovery Time
XI
Set-up Time
Commercial
IDT7200L35
IDT7201LA35
IDT7202LA35
Min.
Max.
—
45
—
10
35
3
5
5
—
45
35
10
18
0
45
35
35
10
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
—
—
35
10
10
22.2
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
45
45
45
30
30
—
30
30
45
45
—
35
35
—
—
—
Com'l & Mil.
(2)
IDT7200L50
IDT7201LA50
IDT7202LA50
Min.
Max.
—
65
—
15
50
3
5
5
—
65
50
15
30
5
65
50
50
15
65
50
50
15
—
—
—
—
—
50
—
—
—
—
50
—
—
50
10
15
15
—
50
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
65
65
65
45
45
—
45
45
65
65
—
50
50
—
—
—
Military
(2)
IDT7201LA80
Min.
Max.
—
100
—
20
80
3
5
5
—
100
80
20
40
10
100
80
80
20
100
80
80
20
—
—
—
—
—
80
—
—
—
—
80
—
—
80
10
15
10
—
80
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
100
60
60
—
60
60
100
100
—
80
80
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
—
30
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
30
30
—
30
30
40
40
—
30
30
—
—
—
3
5
5
—
40
30
10
18
0
40
30
30
10
40
30
30
10
—
—
—
—
—
30
—
—
—
—
30
—
—
30
10
10
Write Pulse High to Data Bus at Low Z
(4, 5)
NOTES:
1. Timings referenced as in AC Test Conditions
2. Military speed grades of 50ns and 80ns are only available for IDT7201LA.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5
APRIL 3, 2006
FPGA/CPLD
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