16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
SST31VF201 / 401 / 8012Mb/4Mb/8Mb Flash (x16) + 1MbSRAM (x16) ComboMemories
Preliminary Specifications
FEATURES:
• Flash Organization: 1M x16
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– SST34HF16x1: 12Mbit + 4 Mbit
– SST34HF16x2: 4 Mbit + 12 Mbit
• SRAM Organization:
– 2 Mbit: 256K x8 or 128K x16
– 4 Mbit: 512K x8 or 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
– Auto Low Power Mode: 20 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 1 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
– Internal
V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Common Flash Memory Interface
(CFI)
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 48-ball LFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST34HF162x/164x ComboMemory devices inte-
grate a 1M x16 CMOS flash memory bank with a 256K x8/
128K x16 or 512K x8/ 256K x16 CMOS SRAM memory
bank in a Multi-Chip Package (MCP). These devices are
fabricated using SST’s proprietary, high-performance
CMOS SuperFlash technology incorporating the split-gate
cell design and thick oxide tunneling injector to attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF162x/164x devices are ideal for
applications such as cellular phones, GPSs, PDAs and
other portable electronic devices in a low power and small
form factor system.
The SST34HF162x/164x features dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 4 Mbits and 12 Mbits
with top or bottom sector protection options for storing boot
code, program code, configuration/parameter data and
user data.
©2001 Silicon Storage Technology, Inc.
S71172-03-000 7/01
523
1
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF162x/164x devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years. With high performance
Word-Program, the flash memory banks provide a typical
Word-Program time of 14 µsec. The entire flash memory
bank can be erased and programmed word-by-word in typ-
ically 8 seconds for the SST34HF162x/164x, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent flash write, the SST34HF162x/164x
devices contain on-chip hardware and software data pro-
tection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Concurrent SuperFlash and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
SRAM bank enable signal, BES1# and BES2, selects the
SRAM bank. The flash memory bank enable signal, BEF#,
has to be used with Software Data Protection (SDP) com-
mand sequence when controlling the Erase and Program
operations in the flash memory bank. The memory banks
are superimposed in the same memory address space
where they share common address lines, data lines, WE#
and OE# which minimize power consumption and area.
Bus contention is eliminated as the device will not recog-
nize both bank enables as being simultaneously active.
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF162x/
164x are offered in both commercial and extended temper-
atures and a small footprint micro ball grid array (µBGA)
package to meet board space constraint requirements.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
Bank 1
Read
Write
Write
No Operation
Write
No Operation
Bank 2
Write
Read
No Operation
Write
No Operation
Write
SRAM
No Operation
No Operation
Read
Read
Write
Write
Note:
For the purposes of this table, write means to Block-, Sector,
or Chip-Erase, or Word-Program as applicable to the
appropriate bank.
Flash Read
The Read operation of the SST34HF162x/164x is
controlled by BEF# and OE#, both have to be low for
the system to obtain data from the outputs. BEF# is
used for device selection. When BEF# is high, the
chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high
impedance state when either BEF# or OE# is high.
Refer to the Read cycle timing diagram for further
details (Figure 8).
Device Operation
The SST34HF162x/164x uses BES1#, BES2 and BEF# to
control operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will result
and the device may suffer permanent damage. All address,
data, and control lines are shared by flash and SRAM
memory banks which minimizes power consumption and
loading. The device goes into standby when BEF# and
BES1# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high and BES2 is low.
The SST34HF162x/164x also have the
Auto Low Power
mode which puts the flash memory in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the I
DD
active read current to typi-
cally 4 µA. The device exits the Auto Low Power mode with
any address transition or control signal transition used to
initiate another read cycle, with no access time penalty.
Flash Word-Program Operation
The SST34HF162x/164x are programmed on a word-by-
word basis. Before Program operations, the memory must
be erased first. The Program operation consists of three
steps. The first step is the three-byte load sequence for
Software Data Protection. The second step is to load word
address and word data. During the Word-Program opera-
tion, the addresses are latched on the falling edge of either
BEF# or WE#, whichever occurs last. The data is latched
on the rising edge of either BEF# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or
BEF#, whichever occurs first. The Program operation, once
initiated, will be completed within 10 µs. See Figures 9 and
10 for WE# and BEF# controlled Program operation timing
diagrams and Figure 23 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Concurrent Read/Write Operation
Dual bank architecture of SST34HF162x/164x devices
allows the Concurrent Read/Write operation whereby the
user can read from one bank while program or erase in the
other bank. This operation can be used when the user
needs to read system code in one bank while updating
data in the other bank. See Figures 1 and 2 for Dual-Bank
Memory Organization.
©2001 Silicon Storage Technology, Inc.
S71172-03-000 7/01
523
2
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
Flash Sector/Block-Erase Operation
The Sector/Block-Erase operation allows the system to
erase the device on a sector-by-sector or block-by-block
basis. The SST34HF162x/164x offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 1 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. See Figures 14
and 15 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
i.e., valid data may appear to conflict with either DQ
7
or
DQ
6
. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
write cycle, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The SST34HF162x/164x includes a Ready/Busy# (RY/
BY#) output signal. During any SDP initiated operation,
e.g., Erase, Program, CFI or ID Read operation, RY/BY# is
actively pulled low, indicating a SDP controlled operation is
in Progress. The status of RY/BY# is valid after the rising
edge of fourth WE# (or CE#) pulse for Program operation.
For Sector-, Block- or Bank-Erase, the RY/BY# is valid after
the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an
open drain output that allows several devices to be tied in
parallel to V
DD
via an external pull up resistor. Ready/
Busy# is in high impedance whenever OE# or CE# is high
or RST# is low.
Flash Chip-Erase Operation
The SST34HF162x/164x provide a Chip-Erase operation,
which allows the user to erase all unprotected sectors/
blocks to the “1” state. This is useful when the device must
be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 4 for the command sequence, Figure 13 for timing
diagram, and Figure 26 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Flash Data# Polling (DQ
7
)
When the SST34HF162x/164x are in the internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles. During internal Erase operation, any attempt to
read DQ
7
will produce a ‘0’. Once the internal Erase opera-
tion is completed, DQ
7
will produce a ‘1’. The Data# Polling
(DQ
7
) is valid after the rising edge of fourth WE# (or BEF#)
pulse for Program operation. For Sector-, Block- or Chip-
Erase, the Data# Polling (DQ
7
) is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 11 for Data# Poll-
ing (DQ
7
) timing diagram and Figure 24 for a flowchart.
Flash Write Operation Status Detection
The SST34HF162x/164x provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
write cycle time. The hardware detection uses the
Ready/Busy# (RY/BY#) pin. The software detection
includes two status bits: Data# Polling (DQ
7
) and Toggle
Bit (DQ
6
). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal
Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ
7
) or Toggle Bit (DQ
6
) read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
©2001 Silicon Storage Technology, Inc.
Flash Toggle Bits (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next oper-
ation. The Toggle Bit (DQ
6
) is valid after the rising edge
of fourth WE# (or BEF#) pulse for Program operation.
For Sector-, Block- or Chip-Erase, the Toggle Bit (DQ
6
) is
valid after the rising edge of sixth WE# (or BEF#) pulse.
See Figure 12 for Toggle Bit timing diagram and Figure
24 for a flowchart.
S71172-03-000 7/01
523
3
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
Data Protection
The SST34HF162x/164x provide both hardware and
software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to Read mode within T
RC
. The contents of
DQ
15
-DQ
8
are “Don’t Care” during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The SST34HF162x/164x also contain the CFI information
to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-
byte sequence, same as Software ID Entry command with
98H (CFI Query command) to address 555H in the last
byte sequence. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses
given in Tables 5 through 7. The system must write the CFI
Exit command to return to Read mode from the CFI Query
mode.
Hardware Block Protection
The SST34HF162x/164x provide a hardware block protec-
tion which protects the outermost 4 KWords in the larger
bank.The block is protected when WP# is held low. See
Figures 1 and 2 for Block-Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
Product Identification
The product identification mode identifies the devices as
the SST34HF162x/164x and manufacturer as SST. This
mode may be accessed by software operations only. The
hardware device ID Read operation, which is typically used
by programmers cannot be used on this device because of
the shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A
9
may damage this device. Users may use the software
product identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 3 and 4 for soft-
ware operation, Figure 16 for the software ID entry and
read timing diagram and Figure 25 for the ID entry com-
mand sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
ADDRESS
Manufacturer’s ID
Device ID
SST34HF1621
0001H
0001H
0001H
0001H
2761H
2762H
2761H
2762H
T1.1 523
Hardware Reset (RST#)
When the RST# input pin is held low for at least T
RP,
any in
progress operation will terminate and the device will return
to Read mode. If an Erase operation has been interrupted,
it needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity. A minimum period
of T
RHR
is required after RST# goes high before a valid
read can take place.
The reset signal must remain low until V
DD
has stabilized.
The device will be ready for operation 20 µs after the
completion of reset and the reset pin is driven high. See
Figures 19 and 20 for timing diagram.
DATA
00BFH
0000H
Software Data Protection (SDP)
The SST34HF162x/164x provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF162x/164x are shipped
©2001 Silicon Storage Technology, Inc.
SST34HF1622
SST34HF1641
SST34HF1642
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
S71172-03-000 7/01
523
4
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 18 for timing waveform and Figure 25 for a
flowchart.
and LBS# provide access to the upper data byte and
lower data byte. See Table 3 for SRAM Read and Write
data byte control modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162x/164x is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. BES1# and BES2 are used for SRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 5, for further details.
SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST34HF162x operates as 256K x8 or 128K x16 CMOS
SRAM, and the SST34HF164x operates as 512K x8 or
256K x16 CMOS SRAM, with fully static operation requir-
ing no external clocks or timing strobes. The CIOs pin
configures the SRAM for x8 or x16 SRAM operation
modes. The SST34HF162x SRAM is mapped into the
first 256 KByte/128 KWord address space of the device,
and the SST34HF164x SRAM is mapped into the first
512 KByte/256 KWord address space. When BES1#,
BEF# are high and BES2 is low, all memory banks are
deselected and the device enters standby. Read and
Write cycle times are equal. The control signals UBS#
SRAM Write
The SRAM Write operation of the SST34HF162x/164x is
controlled by WE# and BES1#, both have to be low, BES2
have to be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagram, Figures 6 and 7, for further details.
F
UNCTIONAL
B
LOCK
D
IAGRAM
AMS - A0
Address
Buffers
SuperFlash Memory
(Bank 1)
RST#
BEF#
WP#
SA
LBS#
UBS#
WE#
OE#
BES1#
BES2
CIOs
RY/BY#
SuperFlash Memory
(Bank 2)
Control
Logic
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
Address
Buffers
AMS = Most significant address
2 Mbit or 4 Mbit
SRAM
503 ILL B1.1
©2001 Silicon Storage Technology, Inc.
S71172-03-000 7/01
523
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
