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5962R9661501VEC

产品描述4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16
产品类别逻辑    逻辑   
文件大小109KB,共10页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

5962R9661501VEC概述

4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16

5962R9661501VEC规格参数

参数名称属性值
零件包装代码DIP
包装说明DIP, DIP16,.3
针数16
Reach Compliance Codecompliant
其他特性1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH; RADIATION HARDENED
系列4000/14000/40000
JESD-30 代码R-CDIP-T16
JESD-609代码e4
长度19.05 mm
负载电容(CL)50 pF
逻辑集成电路类型D LATCH
最大I(ol)0.00064 A
位数1
功能数量1
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
输出极性TRUE
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装等效代码DIP16,.3
封装形状RECTANGULAR
封装形式IN-LINE
电源5/15 V
Prop。Delay @ Nom-Sup608 ns
传播延迟(tpd)608 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度5.08 mm
最大供电电压 (Vsup)18 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量100k Rad(Si) V
触发器类型LOW LEVEL
宽度7.62 mm
Base Number Matches1

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CD4099BMS
December 1992
CMOS 8-Bit Addressable Latch
Pinout
CD4099BMS
TOP VIEW
Features
• High Voltage Type (20V Rating)
• Serial Data Input
• Active Parallel Output
Q7
1
2
16 VDD
15 Q6
14 Q5
13 Q4
12 Q3
11 Q2
10 Q1
9 Q0
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
RESET
DATA 3
WRITE DISABLE
A0
A1
A2
VSS
4
5
6
7
8
Functional Diagram
Applications
• Multi-Line Decoders
• A/D Converters
A0
A1
WRITE DISABLE
DATA
5
4
3
9
10
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
8
6
7
DECODER
8 LATCHES
12
13
14
15
Description
CD4099BMS 8-bit addressable latch is a serial input, parallel
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit
is addressed (by means of inputs A0, A1, A2) and when
WRITE DISABLE is at a low level. When WRITE DISABLE is
high, data entry is inhibited; however, all 8 outputs can be
continuously read independent of WRITE DISABLE and
address inputs.
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a
high level. When RESET is at a high level, and WRITE DIS-
ABLE is at a low level, the latch acts as a 1 of 8 demulti-
plexer; the bit that is addressed has an active output which
follows the data input, while all unaddressed bits are held to
a logic “0” level.
The CD4099BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
A2
RESET
VDD = 16
VSS = 8
2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3333
7-494

5962R9661501VEC相似产品对比

5962R9661501VEC CD4099BFMSR 5962R9661501VXC
描述 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP16, CERAMIC, FP-16
零件包装代码 DIP DIP DFP
包装说明 DIP, DIP16,.3 FRIT SEALED, CERAMIC, DIP-16 DFP, FL16,.3
针数 16 16 16
Reach Compliance Code compliant not_compliant compliant
其他特性 1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH; RADIATION HARDENED 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH; RADIATION HARDENED
系列 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 代码 R-CDIP-T16 R-GDIP-T16 R-CDFP-F16
JESD-609代码 e4 e0 e4
负载电容(CL) 50 pF 50 pF 50 pF
逻辑集成电路类型 D LATCH D LATCH D LATCH
最大I(ol) 0.00064 A 0.00036 A 0.00064 A
位数 1 1 1
功能数量 1 1 1
端子数量 16 16 16
最高工作温度 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C
输出极性 TRUE TRUE TRUE
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DIP DFP
封装等效代码 DIP16,.3 DIP16,.3 FL16,.3
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE FLATPACK
电源 5/15 V 5/15 V 5/15 V
Prop。Delay @ Nom-Sup 608 ns 540 ns 608 ns
传播延迟(tpd) 608 ns 540 ns 608 ns
认证状态 Not Qualified Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
座面最大高度 5.08 mm 3.05 mm 2.92 mm
最大供电电压 (Vsup) 18 V 18 V 18 V
最小供电电压 (Vsup) 3 V 3 V 3 V
标称供电电压 (Vsup) 5 V 5 V 5 V
表面贴装 NO NO YES
技术 CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY
端子面层 GOLD Tin/Lead (Sn/Pb) GOLD
端子形式 THROUGH-HOLE THROUGH-HOLE FLAT
端子节距 2.54 mm 2.54 mm 1.27 mm
端子位置 DUAL DUAL DUAL
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
触发器类型 LOW LEVEL LOW LEVEL LOW LEVEL
宽度 7.62 mm 7.62 mm 6.73 mm
Base Number Matches 1 1 1
长度 19.05 mm 13.97 mm -
厂商名称 - Renesas(瑞萨电子) Renesas(瑞萨电子)

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