HCTS373T
TM
Data Sheet
July 1999
FN4628.1
Radiation Hardened Octal Transparent
Latch, Three-State
Intersil’s Satellite Applications
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCTS373T is a Radiation Hardened Octal
Transparent Three-State Latch with an active-low output
enable. The outputs are transparent to the inputs when the
Latch Enable (LE) is HIGH. When the Latch Enable (LE)
goes LOW, the data is latched. The Output Enable (OE)
controls the three-state outputs. When the Output Enable
(OE) is HIGH, the outputs are in the high impedance state.
The latch operation is independent of the state of the Output
Enable.
Flow
TM
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened CMOS SOS
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- V
IL
= 0.8V Max
- V
IH
= V
CC/2
Min
• Input Current Levels Ii
≤
5mA at V
OL
, V
OH
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCTS373T are
contained in SMD 5962-95747.
A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Pinouts
HCTS373T (SBDIP), CDIP2-T20
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
Ordering Information
ORDERING
NUMBER
5962R9574701TRC
5962R9574701TXC
PART
NUMBER
HCTS373DTR
HCTS373KTR
TEMP.
RANGE
(
o
C)
-55 to 125
-55 to 125
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
D3
Q3
GND 10
HCTS373T (FLATPACK), CDFP4-F20
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HCTS373T
Die Characteristics
DIE DIMENSIONS:
(2743µm x 2692µm x 533µm
±51µm)
108 x 106 x 21mils
±2mil
METALLIZATION:
Type: Al Si
Thickness: 11k
Å
±1k
Å
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13k
Å
±2.6k
Å
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
376
PROCESS:
CMOS SOS
Metallization Mask Layout
HCTS373T
D0
(3)
Q0
(2)
OE
(1)
V
CC
(20)
Q7
(19)
(18) D7
D1 (4)
(17) D6
Q1 (5)
(16) Q6
Q2 (6)
(15) Q5
D2 (7)
(14) D5
(8)
D3
(9)
Q3
(10)
GND
(11)
LE
(12)
Q4
(13)
D4
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCTS373 is TA14403A.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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