Galileo
Technology, Inc.
FEATURES
System Controller
GT- 32090
For i960JX Processors
Preliminary, Rev. 2.0
March 1996
NOTE: Always contact Galileo Technology for
possible updates before starting a design.
• Integrated system controller for embedded applica-
tions
• Supports the i960JX family of CPUs
• 16-33MHz bus frequency
• Flexible DRAM controller
- Page mode and EDO DRAMs
- 128MByte address space
- 256K-4M device depth
- 1-4 banks supported directly
- Up to 8 banks supported indirectly
- 32-bit data width
- Non-interleaved
- Different size for each bank
- Zero wait state to first data at 16 and 20MHz
- One wait state to first data and no wait state to burst
data at 25MHz
- Two wait states to first data and no wait state to
burst data at 33MHz
• Flexible AD bus device controller
- 128MByte address space
- 4 chip selects
- Per bank programmable timing
- Supports several types of standard memories
(ROM / Flash / SRAM) and I/O controllers
- External wait support
- 8-, 16-, and 32-bit device (and boot) support
• High performance DMA
- Three independent channels
- Chaining via linked lists of records
- Transfers through a 16-byte internal FIFO or fly-by
- Moves data between SIO, memory, and devices
- Packing and unpacking of 8-bit and 16-bit data to/
from the SIO bus into 32-bit data on the CPU bus
- Packing and unpacking from/to the SIO bus con-
current with AD bus activity
- Fixed and round robin programmable priorities
• Simple I/O bus (SIO bus)
- Simple Read/Write bus for glueless interface to low
cost peripherals
- 8/16-bit wide bus
- Four chip selects
- Programmable timing
- External wait support
• PCMCIA
- Supports two PCMCIA devices directly
• JTAG
• 5V
• 160 PQFP
External
Agent
i960JX
AD Bus
32
Address &
Control
373
DRAM
Flash
Address
ADBusReq
ADBusGnt
GT-32090
Control
Control
SCSI
16
Network
PCMCIA
Card
UART
Data
SIO Bus
1735 N. First St. #308, San Jose, CA 95112, Tel (408)451-1400, Fax (408)451-1404
1
GT-32090 System Controller For i960JX Processors
OVERVIEW
The GT-32090 is a low cost, highly integrated single-chip
System Controller for the i960Jx Family. It provides high
system performance, while reducing cost, complexity,
device count, and board space. The GT-32090 controls
two separate and independent buses, the CPU’s 16 to
33MHz 32-bit wide address/data bus, and a 16-bit I/O
bus. The two buses can work concurrently at different fre-
quencies.
The DRAM Controller supports up to 128MBytes of stan-
dard or EDO DRAM. It supports up to four 32-bit wide
banks directly, or up to eight banks indirectly, with zero
wait states to first data or burst data at 16 and 20MHz. At
25 and 33MHz, there is one wait state and two wait
states respectively, to first data, and at both frequencies
there are no wait states to burst data. Various refresh and
addressing modes are supported.
The Device Controller supports up to 4 devices directly,
and includes various programmable timing and wait state
mechanisms that can be setup individually for each
device. Typical devices supported include DRAM, ROM,
Flash, and SRAM, as well as high-performance master
peripherals.
The powerful three-channel DMA Controller has data
alignment capabilities and sophisticated chaining support
via link lists. The DMA can move data between devices
on the CPU bus, or between devices on the CPU bus and
devices on the I/O bus. DMA transfers can go through an
on-board 16-byte FIFO, or directly if in fly-by mode.
Packing and unpacking of 8-bit and 16-bit data from/to
the I/O bus occurs concurrently with activity on the CPU
bus, increasing overall system bandwidth.
The I/O bus is a simple 16-bit read/write bus that inter-
faces to a large variety of low cost support components
like UARTs, SCSI controllers, Ethernet controllers, and
other devices. The I/O bus supports 8- or 16-bit peripher-
Galileo
Technology, Inc.
als, as well as slave DMA and PCMCIA devices. Three 4-
byte FIFOs provide efficient support for the gathering of
8-bit or 16-bit data to/from different peripherals, in the
endianess chosen by the designer.
The GT-32090 includes a direct interface to two 8-bit or
16-bit PCMCIA slots.
REFERENCE DESIGN
Galileo makes available the Galileo-5 Evaluation and
Development System, an ISA card which greatly facili-
tates the development of embedded control systems
based on the i960JA/JD/JF Intel processors.
The centerpiece of the system is the GT-32090 System
Controller, which integrates most of the core logic neces-
sary in embedded applications.
The Galileo-5 board serves two main objectives:
a) It allows customers to easily evaluate the performance
of a GT-32090 based system, using their own software,
as opposed to generic benchmarks.
b) It greatly facilitates and expedites the development of
the final product, since hardware designers can use its
design as a reference and software designers can use it
to start porting software ahead of their own hardware
platform.
The shipping configuration of the Galileo-5 includes a
33MHz i960JA CPU, 4MBytes of DRAM, sockets for
2MBytes of Flash, a 512KByte EPROM, a DUART, Intel
MON960 software, and 2 PCMCIA sockets. Jumpers
allow customers to evaluate a large variety of system
configurations, and expansion connectors allow cus-
tomer-designed options to be easily interfaced to.
The Galileo-5 can either be used in stand-alone fashion,
or it can be plugged directly into an ISA slot of standard
personal computers.
CPU Interface
DMA Arbiter
Byte Alignment
DMA CHannel 1
AD Bus
Device
Controller
DMA CHannel 2
DMA CHannel 3
16
Byte
FIFO
DRAM
Controller
Linked List Control
4-Byte
Gathering
FIFO
4-Byte
Gathering
FIFO
4-Byte
Gathering
FIFO
16-Bit
Bypass
Path
PCMCIA
Control
I/O Arbiter
JTAG
16-Bit I/O Bus
SIO
Device
Control
2
Galileo
Technology, Inc.
GT-32090 System Controller For i960JX Processors
1
1.1
PIN INFORMATION
Logic Symbol
ADBusReq
ADBusGnt
DMAReq[2:0]
DMAAck[2:0]*
DMAInt[2:0]*
3
3
3
GT-32090
DMA
ALE
W/R*
ADS*
HoldA
CPU
4
Hold
RdyRcv*
SBE[1:0]*
SCS[3:0]*
SWr*
SRd*
SWait*
2
4
BE[3:0]*
AD[31:0]
32
SIO
11
DAdr[10:0]
4
RAS[3:0]*
16
2
4
P/SData[15:0]
P/SAddr[1:0]
DRAM
CAS[3:0]*
DWr*
LE*
LRdOE*
LWrOE*
BootCS*
IOWrA*
IORdA*
WrEnA*
OEA*
WaitA*
CardEnA[2:1]*
2
PCMCIA
Card A
3
DevCS[2:0]*
WrEn[3:0]*
Ready*
BufOE*
Device
4
IOWrB*
IORdB*
WrEnB*
OEB*
WaitB*
CardEnB[2:1]*
Test*
HiZAll*
2
JTDI
JTClk
Clock
PCMCIA
Card B
Misc.
Rst*
JTAG
SCAN
JTMS
JTRst*
JTDO
3
GT-32090 System Controller For i960JX Processors
Galileo
Technology, Inc.
1.2
Pin Assignment Table
Pin Name
CPU Interface
AD[31:0]
Type
I/O
Description
Address/Data Bus:
Multiplexed address and data bus for commu-
nication between the processor, devices, DRAM, any external
agent, and the GT-32090.
Address Latch Enable:
A strobe for latching the address into the
GT-32090 and into external latches for devices, PCMCIA cards, and
SIO bus peripherals. It is an input during a CPU or external agent
access, and an output during a DMA access.
Address Strobe:
Indicates a valid address and the start of a new
bus access. It is an input during a CPU or external agent access,
and an output during a DMA access.
Byte Enable:
Selects which of the four bytes on the AD bus partici-
pate in the current bus access. It is an input during a CPU or exter-
nal agent access, and an output during a DMA access.
Hold:
A request from the GT-32090 to acquire the AD bus.
Hold Acknowledge:
An indication by the CPU that it has relin-
quished the AD bus to the GT-32090.
Ready/Recover:
Indicates when the data on the AD bus can be
sampled or removed. During a device turn-off time, it indicates to
the CPU not to drive the address on the AD bus.
Write/Read:
Specifies if the access is a write or a read access. It is
an input during a CPU or external agent access, and an output dur-
ing a DMA access. Used also to control the direction of the bi-direc-
tional transceiver for the devices on the AD bus.
DRAM Address/Device Burst Address:
Eleven multiplexed
address bits to the DRAM. DAdr[1:0] provides the word burst
address (same meaning as the CPU’s A3, A2 pins) for all 32-bit
accesses, be they to DRAM or to devices.
Row Address Select:
Supports four banks of DRAM.
Column Address Select:
Supports byte writes to DRAM.
DRAM Write:
Signals a write access to the DRAM.
Latch Enable:
When active, latches the DRAM data into external
latches.
Latch Read Output Enable:
When active, outputs the data from
the DRAM’s external latches onto the AD bus.
Latch Write Output Enable:
When active, outputs the data from
the DRAM’s external latches onto the DRAM’s data pins.
Write Enable:
Byte write enable to devices on the AD bus.
Device Chip Select:
Programmable chip select signals to devices
on the AD bus.
Boot Chip Select:
Programmable chip select signal to the boot
device on the AD bus.
ALE
I/O
ADS*
I/O
BE[3:0]*
I/O
Hold
HoldA
RdyRcv*
O
I
O
W/R*
I/O
DRAM
DAdr[10:0]
O
RAS[3:0]*
CAS[3:0]*
DWr*
LE*
LRdOE*
LWrOE*
AD Bus Devices
WrEn[3:0]*
DevCS[2:0]*
BootCS*
O
O
O
O
O
O
O
O
O
4
Galileo
Technology, Inc.
GT-32090 System Controller For i960JX Processors
Pin Name
Ready*
BufOE*
Type
I
O
Description
Ready:
When not active, it extends the access to a device on the
AD bus by adding wait cycles.
Buffer Output Enable:
This signal has similar functionality to the
DEN* signal of the i960JX, but is active during accesses to devices
only. It is active during the data phase of accesses to devices on the
AD bus. It is used with the W/R* to control external data transceiv-
ers.
PCMCIA & SIO
Shared Signals
P/SAddr[1:0]
P/SData[15:0]
SIO Interface
SBE[1:0]*
SCS[3:0]*
SRd*
SWr*
SWait*
PCMCIA Card A
CardEnA[2:1]*
OEA*
WaitA*
WrEnA*
IORdA*
IOWrA*
PCMCIA Card B
CardEnB[2:1]*
OEB*
WaitB*
WrEnB*
IORdB*
IOWrB*
DMA
ADBusReq
I
Bus Request:
Signals a request from the external agent to the GT-
32090 for acquisition of the AD bus.
O
O
I
O
O
O
Card Enable B:
CardEnB[1] enables the even address bytes, and
CardEnB[2] enables the odd address bytes.
Output Enable B:
Controls the output of data from card.
Wait B:
Extends bus cycle, used to generate wait states by the
card.
Write Enable B:
Indicates write accesses by the GT-32090 to the
card.
I/O Read B:
Activated to read data from the card’s I/O space.
I/O Write B:
Activated to write data to the card’s I/O space.
O
O
I
O
O
O
Card Enable A:
CardEnA[1] enables the even address bytes, and
CardEnA[2] enables the odd address bytes.
Output Enable A:
Controls the output of data from card.
Wait A:
Extends bus cycle, used to generate wait states by the
card.
Write Enable A:
Indicates write accesses by the GT-32090 to the
card.
I/O Read A:
Activated to read data from the card’s I/O space.
I/O Write A:
Activated to write data to the card’s I/O space.
O
O
O
O
I
SIO Byte Enable:
Selects which of the two bytes on the SIO bus
participates in the current data transfer.
SIO Chip Select:
Chip Select for devices on the SIO bus.
SIO Read:
Active during a read from a device on the SIO bus.
SIO Write:
Active during a write to a device on the SIO bus.
SIO Wait:
Extends bus cycle, used to generate wait states by SIO
devices.
O
I/O
PCMCIA/SIO Address:
Byte and half-word addresses for PCMCIA
and SIO accesses.
Data Bus:
Shared data bus for SIO and PCMCIA devices.
5
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