SRAM
Austin Semiconductor, Inc.
64K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89524
• MIL-STD-883
MT5C2565
PIN ASSIGNMENT
(Top View)
FEATURES
High Speed: 12, 15, 20, 25, 35, and 45ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
•
•
•
•
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A15
A14
A13
A12
A11
A10
NC
NC
DQ4
DQ3
DQ2
DQ1
WE\
A1
A0
NC
Vcc
NC
3 2 1 28 27
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
1 0
A9
1 1
CE\
1 2
13 14 15 16 17
DQ1
WE\
NC
Vss
OE\
26
25
24
23
22
21
20
19
18
28-Pin DIP (C)
(300 MIL)
28-Pin LCC (EC)
A15
A14
A13
A12
A11
A10
DQ4
DQ3
DQ2
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
MARKING
-15
-20
-25
-35
-45
-55*
-70*
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) and output
enable (OE\) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished
when WE\ remains HIGH and CE\ and OE\ go LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power
requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
C
EC
No.108
No. 204
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
MT5C2565
A12 A11
A11 A10
A8
A3
A2
A1
A0
A8
A3
A2
A1
A0
262,144-BIT
MEMORY ARRAY
I/O CONTROL
A10 A12
ROW DECODER
DQ4
DQ1
(LSB)
(LCC)
COLUMN DECODER
(LSB)
OE\
WE\
POWER
DOWN
CE\
A7
A6
A5
A4
A9
A15
A14
A13
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\
X
L
H
X
CE\
H
L
L
L
WE\
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss..................................-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.............................-0.5V to +7V
Storage Temperature......................................................-65
o
C to +150
o
C
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................50mA
Lead Temperature (soldering 10 seconds)....................................+260
o
C
Junction Temperature..................................................................+175
o
C
MT5C2565
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYM
V
IH
V
IL
MIN
2.2
-0.5
-10
-10
2.4
MAX
V
CC
+0.5
0.8
10
10
UNITS
V
V
µA
µA
V
NOTES
1
1, 2
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
=-4.0mA
I
OL
=8.0mA
IL
I
IL
O
V
OH
V
OL
1
1
0.4
MAX
-25
120
V
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
CE\ = 2.4V, OE\ = 2.4V,
V
CC
= MAX, f = 0 Hz
CE\ > V
CC
-0.3V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz
"L" Version Only
SYM
I
cc
-15
160
-20
150
-35
120
-45
120
UNITS NOTES
mA
3
I
SBT2
40
40
20
20
20
mA
I
SBC2
I
SBC2
20
10
20
10
10
10
10
10
10
10
mA
mA
CAPACITANCE
DESCRIPTION
Input Capacitance
Output Capacitance
CONDITIONS
T
A
= 25 C, f = 1MHz
V
CC
= 5V
o
SYM
C
I
C
O
MAX
11
11
UNITS
pF
pF
NOTES
4
4
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C2565
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-15
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
15
15
15
3
3
8
8
0
9
15
10
10
0
0
10
9
0
0
7
20
15
15
0
0
15
10
0
0
10
0
9
25
20
20
0
0
20
15
0
0
15
3
3
10
10
0
15
35
25
25
0
0
25
20
0
0
15
20
20
20
3
3
15
15
0
20
45
30
30
0
0
30
20
0
0
20
25
25
25
3
3
15
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
35
3
3
20
30
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
4
4
7
6, 7
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
+5V
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C2565
+5V
480
480
Q
255
5 pF
Q
255
30pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as
in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
1.
2.
3.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
*for -25 and slower only
CONDITIONS
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
SYM
V
DR
I
CCDR
t
CDR
t
R
MIN
2
MAX
---
1
UNITS
V
mA
ns
ns
NOTES
*
4
4, 11
0
t
RC
---
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321
4321
4321
4321
321
21
321
321
3
CE\
V
IH
V
IL
2165
43
87
4365
21214321
87
23214321
87
41214321
21214321
4365
8765
87654321
4321
3 1
87654321
4321
4321
321
321
87654321
4321
321
2
87654321
DON’T CARE
UNDEFINED
嵌入式系统
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