10 Gbit/s
Receiver, CDR
and DeMUX
GD16584
Preliminary
General Description
GD16584 is a 9.95328 Gbit/s Receiver
chip for use in SDH STM-64 and SONET
OC-192 optical communication systems.
GD16584 is a Clock and Data Recovery
IC with:
u
an on-chip VCO
u
a Bang-Bang Phase Detector
u
a 1:16 De-multiplexer
u
a Lock Detect
u
a Phase and Frequency Detector.
Clock and data are regenerated by using
on-chip a
Phase Locked Loop
(PLL) with
an external loop filter.
The VCO frequency is controlled by one
of the two Phase and Frequency Detec-
tors in order to ensure capture and lock
to the line data rate. The Lock Detector
circuit monitors the VCO frequency and
determines when the VCO is within the
locking range. When the frequency devi-
ates more than 500 ppm from the refer-
ence clock, GD16584 automatically
switches the phase and frequency detec-
tor into the PLL loop. In the auto lock
mode the locking range is selectable be-
tween 500 or 2000 ppm.
VCO
VCTL
Features
When the VCO frequency is within the
locking range, the Bang-Bang Phase De-
tector takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A
±40
mV
Decision Threshold Control
(DTC) is pro-
vided at the 10 Gbit/s input.
The 10 Gbit/s input data is sampled and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock. The clock
and data outputs are LVDS compatible.
GD16584 is manufactured in a Silicon Bi-
polar process.
GD16584 operates from a -5.2 V and
+ 3.3 V supply voltage for interfacing
LVDS.
The power dissipation is 3.3 W typical.
GD16584 is delivered in an 132 leads
ceramic Ball Grid Array (BGA). The size
of the package is 13 × 13 mm.
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Complete Clock and Data Recovery
IC with auto acquisition.
Low noise VCO with ±5 % tuning
range.
Digital controlled lock to data by a
Bang-Bang Phase Detector.
Automatic capture of the VCO
frequency by a true Phase and
Frequency Detector.
Locking range selectable between
500 or 2000 ppm.
Input Decision Threshold Control
(DTC):
±40
mV.
1:16 DeMUX with differential
622 Mbit/s data outputs.
LVDS compatible clock and data
outputs.
622 MHz Clock output.
155 or 622 MHz Reference Clock.
Dual supply operation: -5.2 V and
+3.3 V.
Power dissipation: 3.3 W (typ).
Silicon Bipolar technology.
132 leads ceramic BGA 13 × 13 mm
package.
Available in two versions:
– GD16584 for 10 Gbit/s
– GD16588 for 10.66 Gbit/s
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Timing Control
CKOUT
CKOUTN
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DO0
DON0
DI
DIN
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DTC
DTCN
Decision
Threshold
Control
Bang
Bang
Phase
Detector
U
D
1:16
Demultiplexer
Parallel
Output
Data
DO15
DON15
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PHIGH
PLOW
REFCK
REFCKN
Phase
Frequency
Detector
1/4
Applications
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Lock
Detect
LOCK
Telecommunication systems:
– SDH STM-64
– SONET OC-192.
Fibre optic test equipment.
Submarine systems.
Data Sheet Rev.: 05
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RESET
TCK
SEL3
SEL1
SEL2
VCC
VDD
VDDA
VDDO
VEE
VEEA
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Functional Details
The application of GD16584 is as re-
ceiver in SDH STM-64 and SONET
OC-192 optical communication systems.
It integrates:
u
a Voltage Controlled Oscillator (VCO)
u
a Clock and Data Recovery Circuit
u
a Lock Detect Circuit
u
a 1:16 DeMUX
u
a Phase and Frequency Detector
(PFD).
Loop Filter
The external loop filter is made using a
operational amplifier connected to output
pin (PHIGH and PLOW). The characte-
ristics of the phase lock loop are con-
trolled by the loop filter components
hence the op-amp is designed as an inte-
grator by a feedback capacitor and a re-
sistor. The gain-bandwidth of the op-amp
must be larger than the required PLL
bandwidth in order not to limit the PLL.
The recommended op-amp is Analog De-
vices (AD8042) with a gain-bandwidth of
160 MHz sufficient for PLL bandwidth up
to 50 MHz. The op-amp is used single
supplied by –5.2 V. See
Figure 1
for ap-
plication information.
The phase information from the Bang-
Bang phase detector are very high fre-
quency pulses (200 ps pulse width) at
output pins (PHIGH and PLOW). They
are open collector outputs with a 8 mA
current drive and are terminated exter-
nally by 100
Ω
to 0 V. A pre-filtering of
the phase pulses are applied by a paral-
lel 10 pF capacitor (see
Figure 1).
The PCB layout of the external loop filter
and the connecting lines to PHIGH,
PLOW and VCTL are critical for the jitter
performance of the component. The art-
work for the op-amp and the passive
components should be placed very close
to the pins of GD16584 in order to have
connecting lines as short as possible.
Ideally the loop filter components are
placed on the opposite side of the PCB
directly underneath GD16584.
The PCTL pin is available for future use
with a passive loop filter. For more infor-
mation, please contact GIGA.
The Inputs
The input amplifier pin (DI/DIN) is de-
signed as a gain buffer stage with high
sensitivity and internal 50
Ω
resistors ter-
minated to 0 V. After retiming, the data is
de-multiplexed down to 622 Mbit/s by the
1:16 DeMUX. The input data is de- multi-
plexed starting with DO0, DO1...DO15 as
the first received bits.
It is recommended to use the 10 Gbit/s
inputs differentially.
The 10 Gbit/s inputs (DI and DIN) are
not ESD protected
and extra precau-
tions are needed when handling these in-
puts. (Internal 50
Ω
resistors provide
some ESD hardness making the input
low impendance.)
The input voltage decision threshold is
adjustable by pin DTC and DTCN when
connected to a potentiometer. Adjusting
the resistor value of the meter controls
the current into DTC and DTCN. This DC
current is mirrored to the input pin (DI
and DIN) whereby the DC bias voltage at
the input is adjustable by
±40
mV. Opti-
mizing the input decision threshold im-
proves the system input sensitivity by
1-2 dB typical.
The input impedance into DTC and
DTCN is 1.5 kΩ and when not used they
should be de-coupled to 0 V by 100 nF.
The select inputs (SEL1-3, RESET and
TCK) are low speed inputs that can be
connected directly to the supply rails (0 /
-5.2 V).
VCO
The VCO is an LC-type differential oscil-
lator at 10 GHz, voltage controlled by pin
VCTL and with a tuning range of approxi-
mately ±5 %.
With the VCTL voltage at approximately
-3.5 V the VCO frequency is fixed at
9.953 GHz and by changing the voltage
from 0 to -5.2 V the frequency is con-
trolled from 8.9 GHz to 10.2 GHz. The
modulation bandwidth of VCTL is
90 MHz.
PFD
The PFD ensures predictable locking
conditions for the GD16584. It is used
during acquisition and pulls the VCO into
the locking range where the Bang-Bang
Phase Detector acquires lock to the in-
coming bit-stream. The PFD is made with
digital set/reset cells giving it a true
phase and frequency characteristic. The
reference clock input (REFCK/REFCKN)
to the PFD is differential and selectable
between 155 MHz or 622 MHz by SEL3.
The reference clock input is CML input
with 50
Ω
internal termination resistors to
0 V. The reference clock is typically an
X-tal oscillator type as shown on
Figure
1.
The reference clock input should be
used differential for best performance. If
the reference clock is DC coupled the in-
put voltage swing is 0 V (high) and -0.4 V
(low).
The Outputs
The data and clock outputs are LVDS
compatible outputs with internal bias re-
sistors (500
Ω)
to VCC (+3.3 V)
Refer to item “LVDS Compatible Inter-
face” on
page 6.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the VCO clock. If they differ by
more than 500 (or 2000 ppm), it switches
the PFD into the PLL, to pull it back into
the locking range. The status of the lock
circuit is given by output pin (LOCK).
Manual or automatic lock is selected by
SEL1. In auto lock mode, the lock range
±500 or ±2000 ppm is selected by SEL2.
The LOCK output is an open collector
output, so it should be terminated with an
external resistor. The maximum termina-
tion voltage is +3.5 V.
Bang-Bang Phase Detector
The Bang-Bang phase detector is de-
signed as a true digital type producing a
binary output. It samples the incoming
data prior to, in the vicinity of and after
any potential bit transition.
When a transition has occurred, these
three samples tell whether the VCO clock
leads or lags the data. The binary output
is filtered through the (low pass) loop fil-
ter, performing an integration of all poten-
tial bit transitions. Hence the PLL is
controlled by the bit transition point.
Timing
The timing between GD16584 and the
system ASIC at 622 Mbit/s is controlled
by the 622 MHz output clock synchro-
nized with the output data. The clock is
used as the input clock to the ASIC,
clocking the input data into 16 parallel
registers. The timing relation between
clock and data is given by the AC
Characteristics.
Data Sheet Rev.: 05
GD16584
Page 2 of 13
External Circuit
The external circuits needed to make
GD16584 work as a complete clock and
data recovery with automatic acquisition
are:
u
Active loop filter with op-amp
u
An X-tal oscillator or reference clock
(155 MHz or 622 MHz)
Package
GD16584 is packaged in an 132 leads
ceramic BGA (13 × 13 mm).
Thermal Condition
The component dissipates 3.3 W from a
dual voltage supply (–5.2 V and +3.3 V).
The power consumption from the -5.2 V
supply is approximately 2.9 W and 0.4 W
from the +3.3 V supply.
The component conducts most of the
power through the center leads of the
package (all VDD connected leads).
It is important to have a good thermal
connection from the center leads of the
package to the ambient environment to
ensure the case temperature in the range
from 0 to 70 °C.
Power Noise Rejection
In a noisy environment special attention
must be taken as described above to op-
timize the jitter performance and to re-
duce the input sensitivity penalty from
injected noise. The
Power Supply Rejec-
tion Ratio
(PSRR) may be improved by
adding a serial resistor (330
Ω)
and ca-
pacitor (33 nF) from the positive input of
the op-amp to the VEEA power pin (C3,
D3) as shown in
Figure 1.
10.66 Gbit/s Application
A version of the transmitter with a bit rate
of 10.66 Gbit/s for forward error correc-
tion application is available. The part
number is GD16588.
The functionality and the pin-out are
identically to GD16584.
The center frequency of the VCO
(10.66 GHz) is the only difference to
GD16584.
Data Sheet Rev.: 05
GD16584
Page 3 of 13
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