DATASHEET
ISL85009
9A, 3.8V to 18V Input, Synchronous Buck Regulator
The
ISL85009
is a highly efficient, monolithic, synchronous
buck regulator that can deliver 9A of continuous output current
from a 3.8V to 18V input supply. The device uses current mode
control architecture with a fast transient response and
excellent loop stability.
The ISL85009 integrates very low ON-resistance high-side and
low-side FETs to maximize efficiency and minimize external
component count. The minimum BOM and easy layout
footprint are extremely friendly to space constraint systems.
The operation frequency of this device can be set using the
FREQ pin: 600kHz (FREQ = float) and 300kHz (FREQ = GND).
The device can also be synchronized to an external clock up to
1MHz.
Both high-side and low-side MOSFET current limit along with
reverse current limit, fully protect the regulator in an
overcurrent event. Selectable OCP schemes can fit various
applications. Other protections, such as input/output
overvoltage and over-temperature, are also integrated into the
device which give required system level safety in the event of
fault conditions.
The ISL85009 is offered in a space saving 15 Ld 3.5mmx3.5mm
Pb-free TQFN package with great thermal performance and
0.8mm maximum height.
FN8918
Rev.2.00
Jul 31, 2020
Features
• Power input voltage range variable 3.8V to 18V
• PWM output voltage adjustable from 0.6V
• Up to 9A output load
• Prebias start-up, fixed 3ms soft-start
• Selectable f
SW
of 300kHz, 600kHz, and external
synchronization up to 1MHz
• Peak current mode control
- DCM/CCM
- Thermally compensated current limit
- Internal/external compensation
• Open-drain PG window comparator
• Output overvoltage and thermal protection
• Input overvoltage protection
• Integrated boot diode with undervoltage detection
• Selectable OCP schemes
- Hiccup OCP
- Latch-off
• Compact size 3.5mmx3.5mm, 15 Ld TQFN
Related Literature
• For a full list of related documents please visit our web page
-
ISL85009
product page
Applications
• Servers and cloud infrastructure POLs
• IPCs, factory automation, and PLCs
• Telecom and networking systems
• Storage systems
• Test measurement
C
VIN
R
2
R
3
C
1
100
R
1
90
80
70
60
50
40
Vout = 5V, fsw = 600kHz
Vout = 3.3V, fsw = 600kHz
30
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
PVIN
PHASE
GND
VDD BOOT
5
6
L
1
4.5V TO
18V
VOUT
8
C
IN
7
C
OUT
SYNC MODE FREQ PG
1
2
3
4
C
VDD
2.2µF
C
BOOT
100nF
FIGURE 1. TYPICAL APPLICATION SCHEMATIC FOR INTERNAL COMPENSATION
EFFICIENCY (%)
VIN
15
14
VIN EN
9
13
12
11
10
DNC DNC COMP FB
FIGURE 2. EFFICIENCY (V
IN
= 12V)
FN8918 Rev.2.00
Jul 31, 2020
Page 1 of 20
ISL85009
Typical Application Schematic
C
1
C
VIN
C
2
R
3
R
2
VIN
4.5 TO
18V
15
14
VIN EN
9
13
12
11
10
DNC DNC COMP FB
PVIN
PHASE
GND
VDD BOOT
5
6
R
1
L
1
VOUT
C
IN
8
7
SYNC MODE FREQ PG
1
2
3
4
C
OUT
C
VDD
2.2µF
C
BOOT
100nF
FIGURE 3. TYPICAL APPLICATION SCHEMATIC FOR EXTERNAL COMPENSATION
TABLE 1. DESIGN TABLE FOR DIFFERENT OUTPUT VOLTAGE USING INTERNAL COMPENSATION (See
Figure 1)
V
OUT
(V)
V
IN
(V)
FREQ (kHz)
Compensation
C
IN
(µF)
C
OUT
(µF)
L
1
(µH)
R
1
(kΩ)
R
2
(kΩ)
C
1
(pF)
NOTES:
1. The design table is referencing the schematic shown in
Figure 1.
2. Ceramic capacitors are selected for 22µF, 47µF, and 100µF in the table.
3. 560µF (4.5mΩ) low ESR conductive polymer aluminum solid capacitors are selected.
4. Recommend to keep the inductor peak-to-peak current to less than 5A.
1
4.5 to 18
300
Internal
3x22
560 + 3x100
1
100
150
DNP
1.2
4.5 to 18
300
Internal
3x22
560 + 3x100
1
147
147
DNP
1.8
4.5 to 18
600
Internal
3x22
3x100
1
200
100
4.7
3.3
4.5 to 18
600
Internal
3x22
4x47
1.5
365
80.6
3.3
5
6 to 18
600
Internal
3x22
4x47
1.5
365
49.9
3.3
Ordering Information
PART NUMBER
(Notes
5, 6, 7)
ISL85009FRZ-T
ISL85009FRZ-T7A
ISL85009EVAL1Z
NOTES:
5. See
TB347
for details on reel specifications.
6. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
7. For Moisture Sensitivity Level (MSL), please see product information page for
ISL85009.
For more information on MSL, see
TB363.
PART
MARKING
5009
5008
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
TAPE AND REEL
(UNITS)
6k
250
PACKAGE
(RoHS COMPLIANT)
15 Ld 3.5mmx3.5mm TQFN
PKG.
DWG. #
L15.3.5x3.5
FN8918 Rev.2.00
Jul 31, 2020
Page 2 of 20
ISL85009
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL85009
ISL85012
ISL85014
INTERNAL/EXTERNAL COMPENSATION
Yes
Yes
Yes
EXTERNAL FREQUENCY SYNC
Yes
Yes
Yes
CURRENT RATING
9A
12A
14A
Functional Block Diagram
MODE
2
SYNC
1
FREQ
3
VIN
15
HIGH-SIDE
OCP
SCHEME
SETTING
EN
LDO
BOOT
UVP
6 BOOT
5 VDD
UNDERVOLTAGE
LOCKOUT
OSCILLATOR
9 PVIN
CSA
EN 14
PG 4
FAULT
MONITOR
CIRCUITS
0.6V
REFERENCE
SLOPE
COMP
+
+
-
GATE DRIVE
CONTROL
CIRCUIT
EA
VDD
8 PHASE
THERMAL
SHUTDOWN
SOFT-START
CONTROL
+
+
-
7 GND
FB 10
FREQ
800/1200kΩ
30pF
COMP 11
GND DETECTION
CIRCUIT
ZERO CROSS
DETECTOR
AND
NEGATIVE
CURRENT
LIMIT
POSITIVE
LS OCP
13 DNC
12 DNC
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM
FN8918 Rev.2.00
Jul 31, 2020
Page 3 of 20
ISL85009
Pin Configuration
ISL85009
(15 LD 3.5mmx3.5mm TQFN)
TOP VIEW
15
VIN
9
14
EN
13
DNC
12
11
10
FB
DNC COMP
PVIN
8
PHASE
7
GND
PG
4
VDD BOOT
5
6
SYNC MODE FREQ
1
2
3
Pin Descriptions
PIN#
1
PIN
NAME
SYNC
DESCRIPTION
Synchronization and FCCM/DEM selection pin. Connect to VDD or float for Forced Continuous Conduction Mode. Connect to GND
for Diode Emulation Mode in the light-load condition. Connect to an external clock signal for synchronization with the rising edge
trigger.
OCP scheme select pin. Short it to GND for Latch-Off mode. Float it for Hiccup mode.
Default frequency selection pin. Short it to GND for 300kHz. Float it for 600kHz.
Power-good open-drain output. It requires a pull-up resistor (10kΩ to 100kΩ) between PG and VDD or a voltage not exceeding
5.5V. PG pulls high when FB is in the range of ~90% to ~116% of its intended value.
Low dropout linear regulator decoupling pin. The VDD is the internally generated 5V supply voltage and is derived from VIN. The
VDD is used to power all the internal core analog control blocks and drivers. Connect a 2.2µF capacitor from VDD to the board
ground plane. If the V
IN
is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency.
BOOT is the floating bootstrap supply pin for the high-side power MOSFET gate driver. A bootstrap capacitor, usually 0.1µF, is
required between BOOT and PHASE.
Reference of the power circuit. For thermal relief, this pin should be connected to the ground plane by vias.
Switch node connection to the internal power MOSFETs (source of upper FET and drain of lower FET) and the external output
inductor.
Input supply for the PWM regulator power stage. A decoupling capacitor, typically ceramic, is required to be connected between
this pin and GND.
Inverting input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB.
Output of the error amplifier. Compensation network between COMP and FB to configure external compensation. Place a 200Ω
resistor between COMP and GND for internal compensation, which is used to meet most applications.
Do Not Connect to pin. Float the pins in the design.
Enable input. The regulator is held off when this pin is pulled to ground. The device is enabled when the voltage on this pin rises
to about 0.6V.
Input supply for the control circuit and the source for the internal linear regulator that provides bias for the IC.
A decoupling capacitor, typically 1µF ceramic, is required between VIN and GND.
2
3
4
5
MODE
FREQ
PG
VDD
6
7
8
9
10
11
12, 13
14
15
BOOT
GND
PHASE
PVIN
FB
COMP
DNC
EN
VIN
FN8918 Rev.2.00
Jul 31, 2020
Page 4 of 20
ISL85009
Absolute Maximum Ratings
VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22V
PVIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +22V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +22V (40ns)
BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
VDD, COMP, SYNC, PG, FB, MODE, FREQ, SS, IOCP to GND . . . -0.3V to +7V
ESD Rating
Human Body Model (Tested per JS-001-2014). . . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD78E; Class 2, Level A, +125°C). . . . . . . 100mA
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
TQFN Package (Notes
8, 9)
. . . . . . . . . . . . .
33
1.2
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
PVIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V to 18V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 9A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
8.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features, except with
three vias under the GND EPAD strip contacting the GND plane and two vias under the VIN EPAD strip contacting the VIN plane. See
TB379.
9. For
JC
, the case temperature location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specifications are measured at the following conditions: T
J
= -40°C to +125°C, V
IN
= 4.5V to 18V, unless otherwise noted. Typical values are at
T
A
= +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
SUPPLY VOLTAGE
PVIN Voltage Range
VIN Voltage Range
VIN Quiescent Supply Current
VIN Shutdown Supply Current
POWER-ON RESET
PVIN POR Threshold
VIN POR Threshold
EN POR Threshold
VDD POR Threshold
INTERNAL VDD LDO
VDD Output Voltage Regulation Range
VDD Output Current Limit
LDO Dropout Voltage
OSCILLATOR
Nominal Switching Frequency
Nominal Switching Frequency
Minimum On-Time
Minimum Off-Time
Synchronization Range
SYNC Logic Input Low
SYNC Logic Input High
1.2
f
SW1
f
SW2
t
ON
t
OFF
100
FREQ = float
FREQ = GND
I
OUT
= 0mA
540
250
600
280
90
140
660
310
150
170
1000
0.5
kHz
kHz
ns
ns
kHz
V
V
V
IN
= 5V, I
VDD
= 30mA
V
IN
= 6V to 18V, I
VDD
= 0mA to 30mA
4.3
5.0
80
0.65
5.5
V
mA
V
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Hysteresis
Rising edge
Falling edge
2.4
3.4
0.5
0.6
100
3.6
0.7
1.9
4.49
2.9
V
V
V
V
V
mV
V
V
PVIN
VIN
I
Q
I
SD
EN = 2V, FB = 0.64V
EN = GND
3.8
4.5
3
8
18
18
5
13
V
V
mA
µA
SYMBOL
TEST CONDITIONS
MIN
(Note
10)
TYP
MAX
(Note
10)
UNIT
FN8918 Rev.2.00
Jul 31, 2020
Page 5 of 20
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