HN58X24128SR/HN58X24256SR
Two-wire serial interface
128k EEPROM (16-kword
×
8-bit)
256k EEPROM (32-kword
×
8-bit)
ADE-203-1030A (Z)
Rev. 1.0
Apr. 2, 1999
Description
HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 64-byte page programming function to make their write operation faster.
Features
•
Single supply: 1.8 V to 5.5 V
•
Two-wire serial interface (I C
2
TM
serial bus* )
1
•
Clock frequency: 400 kHz
•
Power dissipation:
Standby: 3 µA(max)
Active (Read): 1 mA(max)
Active (Write): 5 mA(max)
•
Automatic page write: 64-byte/page
•
Write cycle time: 10 ms (2.7 V to 5.5 V )/15ms (1.8 V to 2.7 V )
•
Endurance: 10 Cycles (Page write mode)
5
•
Data retention: 10 Years
•
Small size packages: SOP-8pin, TSSOP-14pin
•
Temperature range: –20 to +85°C
Note: 1. I C is a trademark of Philips Corporation.
2
HN58X24128SR/HN58X24256SR
Ordering Information
Type No.
Internal organization
Operating voltage Frequency
1.8 V to 5.5 V
400 kHz
Package
150 mil 8-pin plastic SOP
(FP-8DB)
HN58X24128FPSR 128k bit
(16384
×
8-bit)
HN58X24256FPSR 256k bit
(32768
×
8-bit)
HN58X24128TSR
HN58X24256TSR
128k bit
(16384
×
8-bit)
256k bit
(32768
×
8-bit)
1.8 V to 5.5 V
400 kHz
14-pin plastic TSSOP
(TTP-14D)
Pin Arrangement
8-pin SOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
(Top view)
V
CC
WP
SCL
SDA
A0
A1
NC
NC
NC
A2
V
SS
14-pin TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
(Top view)
V
CC
WP
NC
NC
NC
SCL
SDA
Pin Description
Pin name
A0 to A2
SCL
SDA
WP
V
CC
V
SS
NC
Function
Device address
Serial clock input
Serial data input/output
Write protect
Power supply
Ground
No connection
2
HN58X24128SR/HN58X24256SR
Block Diagram
V
CC
V
SS
High voltage generator
Address generator
X decoder
Memory array
WP
A0, A1, A2
SCL
SDA
Control
logic
Y decoder
Y-select & Sense amp.
Serial-parallel converter
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
Storage temperature range
1
Symbol
V
CC
Vin
Topr
Tstg
Value
–0.6 to +7.0
–0.5* to +7.0*
–20 to +85
–65 to +125
2
3
Unit
V
V
•C
•C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): –3.0 V for pulse width • 50 ns.
3. Should not exceed V
CC
+ 1.0 V.
3
HN58X24128SR/HN58X24256SR
DC Operating Conditions
Parameter
Supply voltage
Input high voltage
Input low voltage
Operating temperature
Symbol
V
CC
V
SS
V
IH
V
IL
Topr
Min
1.8
0
V
CC
×
0.7
–0.3*
–20
1
Typ
—
0
—
—
—
Max
5.5
0
V
CC
+ 1.0
V
CC
×
0.3
85
Unit
V
V
V
V
•C
Notes: 1. V
IL
(min): –1.0 V for pulse width • 50 ns.
DC Characteristics
(Ta = –20 to +85•C, V
CC
= 1.8 V to 5.5 V)
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Read V
CC
current
Write V
CC
current
Output low voltage
Symbol Min
I
LI
I
LO
I
SB
I
CC1
I
CC2
V
OL2
—
—
—
—
—
—
Typ
—
—
1.0
—
—
—
Max
2.0
2.0
3.0
1.0
5.0
0.4
Unit
µA
µA
µA
mA
mA
V
Test conditions
V
CC
= 5.5 V, Vin = 0 to 5.5 V
V
CC
= 5.5 V, Vout = 0 to 5.5 V
Vin = V
SS
or V
CC
V
CC
= 5.5 V, Read at 400 kHz
V
CC
= 5.5 V, Write at 400 kHz
V
CC
= 4.5 to 5.5 V, I
OL
= 1.6 mA
V
CC
= 2.7 to 4.5 V, I
OL
= 0.8 mA
V
CC
= 1.8 to 2.7 V, I
OL
= 0.4 mA
V
CC
= 1.8 to 2.7 V, I
OL
= 0.2 mA
V
OL1
—
—
0.2
V
Capacitance
(Ta = 25•C, f = 1 MHz)
Parameter
Symbol
1
1
Min
—
—
Typ
—
—
Max
6.0
6.0
Unit
pF
pF
Test
conditions
Vin = 0 V
Vout = 0 V
Input capacitance (A0 to A2, SCL, WP) Cin*
Output capacitance (SDA)
Note:
C
I/O
*
1. This parameter is sampled and not 100% tested.
4
HN58X24128SR/HN58X24256SR
AC Characteristics
(Ta = –20 to +85•C, V
CC
= 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
V
IL
= 0.2
×
V
CC
V
IH
= 0.8
×
V
CC
•
Input rise and fall time: • 20 ns
•
Input and output timing reference levels: 0.5
×
V
CC
•
Output load: TTL Gate + 100 pF
Parameter
Clock frequency
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
Bus free time for next mode
Start hold time
Start setup time
Data in hold time
Data in setup time
Input rise time
Input fall time
Stop setup time
Data out hold time
Write cycle time
V
CC
= 2.7 V to 5.5 V
V
CC
= 1.8 V to 2.7 V
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WC
t
WC
Min
—
1200
600
—
100
1200
600
600
0
100
—
—
600
50
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
—
—
50
900
—
—
—
—
—
300
300
—
—
10
15
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
2
2
1
1
1
Notes
Notes: 1. This parameter is sampled and not 100% tested.
2. t
WC
is the time from a stop condition to the end of internally controlled write cycle.
5
FPGA/CPLD
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