Ordering number : EN6870B
LC72713W
SANYO Semiconductors
DATA SHEET
CMOS IC
LC72713W
Overview
Mobile FM Multiplex Broadcast IC
with On-Chip VICS Decoder
The LC72713W is data demodulator ICs for receiving FM multiplex broadcasts for mobile reception in the DARC
format. This IC includes an on-chip bandpass filter for extracting the DARC signal from the FM baseband signal.
It also integrates a decoder circuit that performs the VICS data processing on the same chip and can implement a
compact, multifunction VICS reception system. The LC72713W is an improved version of the LC72710W that
features circuit improvements that allow a single tuner to receive both the VICS data and the dGPS data supported by
the earlier device. Note that a contract with VICS Center is required to evaluate this sample IC and to produce end
products that support VICS.
Functions
Adjustment-free 76kHz SCF bandpass filter
•
Built-in VICS decoder
•
MSK delay detection system based on a 1T delay.
•
Error correction function based on a 2T delay (in the MSK detection stage)
•
Digital PLL based clock regeneration function
•
Shift-register 1T and 2T delay circuits
•
Block and frame synchronization detection circuits
•
Functions for setting the number of allowable BIC errors and the number of synchronization protection operations.
•
Error correction using (272, 190) codes
•
Built-in layer 4 CRC code checking circuit
•
On-chip frame memory and memory control circuit for vertical correction
•
7.2MHz crystal oscillator circuit
•
Two power saving modes: STNBY and EC STOP
•
Dedicated frame synchronization circuit for simultaneous reception of dGPS and VICS data
•
Applications can use either a parallel CPU interface (DMA) or a CCB serial interface.
•
Supply voltage: 4.5 to 5.5V
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
•
CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92607 HKIM 20070822-S00009 / 92001 TN (OT) No.6870-1/29
LC72713W
Specifications
Absolute Maximum Ratings
at Ta=25°C, VSS=0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable output current (total)
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VIN1
VIN2
VOUT1
VOUT2
IOUT1
IOUT2
ITTL
Pd max
Topr
Tstg
A0/CL, A1/CE, A2/DI, RST, STNBY
Pins other than VIN1
DO
Pins other than VOUT1
INT, RDY, DREQ, and D0 to D15
Pins other than IOUT1
Total for all the output pins
Ta
≤
85°C
Conditions
Ratings
-0.3 to +7.0
-0.3 to +7.0
-0.3 to VDD +0.3
-0.3 to +7.0
-0.3 to VDD +0.3
0 to 4.0
0 to 2.0
20
200
--40 to +85
--55 to +125
Unit
V
V
V
V
V
mA
mA
mA
mW
°C
°C
Allowable Operating Ranges
at Ta=-40 to +85°C, VSS=0V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Oscillator frequency
XIN input sensitivity
Input amplitude
[Serial I/O]
Clock low-level period
Clock high-level period
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
CRC4 change time
tCL
tCH
tSU
tHD
tEL
tES
tEH
tLC
tDDO
tCRC
A0/CL
A0/CL
A0/CL, A2/DI
A0/CL, A2/DI
A0/CL, A1/CE
A0/CL, A1/CE
A0/CL, A1/CE
A1/CE
DO, A0/CL
CRC4, A0/CL
277
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
555
0.7
μS
μS
μS
μS
μS
μS
μS
μS
nS
μS
Symbol
VDD
VIH1
VIH2
VIL1
VIL2
FOSC
VXI
VMPX
A0/CL, A1/CE, A2/DI, RST, STNBY
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
Pins for which VIH1 applies
Pins for which VIH2 applies
This IC operates with a frequency precision of
±250
ppm
With a sine wave input to XIN, capacitor coupling,
VDD=+4.5 to +5.5V
With a 100% modulated composite signal input to
MPXIN, VDD=+4.5 to +5.5V
400
150
Conditions
Ratings
min
4.5
0.7VDD
0.7VDD
VSS
VSS
7.2
1500
500
typ
max
5.5
5.5
VDD
0.3VDD
0.3VDD
Unit
V
V
V
V
V
MHz
mVrms
mVrms
No.6870-2/29
LC72713W
Allowable Operating Ranges: Parallel Interface
at Ta=-40 to +85°C, VSS=0V
Parameter
[Parallel I/O]
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
RDY width (corrected output read)
DACK to DREQ delay
DMA cycle wait
RD low-level width (DMA)
tSARD
tHARD
tWRDL1
tWRDL2
tCYRD
tWRDY
tRDH
tSAWR
tHAWR
tCYWR
tWWRL
tWDH
tDRDY
tWDRD1
tWDRD2
tWDRDY
tDREQ
tCYDM
tWRDM
A0/CL, A1/CE, A2/DI, A3, RD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250ns
RD
RD
A0/CL, A1/CE, A2/DI, A3, RD
RDY
RD, DATn
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
WR
WR, DATn
RD, RDY
RD (BUSWD=L 8bits)
RD (BUSWD=H 16bits)
RD (BUSWD=L 8bits)
RD (BUSWD=H 16bits)
RDY (BUSWD=L 8bits)
RDY ((BUSWD=H 16bits)
DREQ, DACK
RD, DREQ
RD
300
20
-20
250
100
150
60
0
20
20
150
200
0
0
300
540
100
300
60
300
210
490
260
420
30
210
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Symbol
Conditions
Ratings
min
typ
max
Unit
Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250ns (minimum).
Electrical Characteristics
at VDD=+4.5 to +5.5V, within the allowable operating ranges
Parameter
Symbol
VOH1
VOH2
VOL1
Low-level output voltage
VOL2
VOL3
High-level input current
Low-level input current
Input resistance
Reference supply voltage output
Bandpass filter center frequency
-3 dB bandwidth
Group delay
Gain
IIH1
IIH2
IIL
RMPX
Vref
Fc
Fbw
Dgd
Gain
ATT1
Stop band attenuation
ATT2
ATT3
ATT4
Output off leakage current
Hysteresis voltage
Internal feedback resistor
Current drain
IOFF
VHYS
Rf
IDD
Conditions
IO=2mA, BCK, FCK, BLOCK, FLOCK,
CRC4, CLK16, DATA
IO=4mA, INT, RDY, DREQ, D0 to D15
IO=2mA, Pins for which VOH1 applies
IO=4mA, Pins for which VOH2 applies
IO=2mA, DO, INT
VIN=5.5V, A0/CL, A1/CE, A2/DI, RST,
STNBY
VIN=VDDD, All input pins other than IIH1
VIN=VSSD, All input pins
MPXIN -Vssa f=100kHz
Vref, Vdda=5V
FLOUT
FLOUT
FLOUT
FLOUT-MPXIN, f=76kHz
FLOUT, f=50kHz
FLOUT, f=100kHz
FLOUT, f=30kHz
FLOUT, f=150kHz
VO=VDDD, DO
A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,
DACK, IOCNT1, IOCNT2, RST, STNBY
XIN, XOUT
25
15
50
50
5.0
0.1VDDD
1.0
18
25
-7.5
20
50
2.5
76.0
19.0
+7.5
Ratings
min
VDD-0.4
VDD-0.4
0.4
0.4
0.4
1.0
1.0
-1.0
typ
max
Unit
V
V
V
V
V
μA
μA
μA
kΩ
V
kHz
kHz
μs
dB
dB
dB
dB
dB
μA
V
MΩ
mA
High-level output voltage
No.6870-3/29
LC72713W
Package Dimensions
unit : mm (typ)
3190A
12.0
10.0
48
49
33
32
64
1
0.5
(1.25)
(1.5)
0.18
16
17
0.15
1.7max
0.1
SANYO : SQFP64(10X10)
Pin Assignment
BUSWD
SP
RST
STNBY
CS
A3
10.0
12.0
0.5
A2/DI
A1/CE
A0/CL
RD
WR
DO
Vssd
Vddd
INT
NC
49
TIN
NC
Vssa
Vref
MPXIN
Vdda
FLOUT
CIN
NC
TPC1
TPC2
TEST
TOSEL1
TOSEL2
Vssd
XIN
64
1
XOUT
Vddd
IOCNT1
IOCNT2
CLK16
DATA
FLOCK
BLOCK
FCK
BCK
CRC4
DREQ
DACK
Vssd
Vddd
RDY
32
D15
D14
D13
D12
D11
D10
D9
LC72713W
D8
D7
D6
D5
D4
D3
D2
D1
D0
16
(Top view)
No.6870-4/29
LC72713W
Block Diagram
BLOCK
FLOCK
BCK
FCK
CLK16
DATA
Vddd
Vssd
1T delay
STNBY
RST
XOUT
XIN
7.2MHz
LPF
Clock
regeneration
2T delay
LPF
MSK correction
circuit
Synchronization
regeneration
Timing
control
Error correction:
layer 2 CRC
PN decoding
Data
Vref
MPXIN
Anti-aliasing
filter
76kHz
BPF
(SCF)
Vdda
Vssa
Vref
Output control (CPU interface) and
layer 4 CRC detection circuit
VICS processing
Address
Memory array
Pin Functions
Pin No.
3
4
13
38
39
40
41
42
43
44
46
45
47
48
60
58
59
61
62
49
5
6
9
10
7
8
11
33
12
16
Pin
IOCNT1
IOCNT2
DACK
WR
RD
A0/CL
A1/CE
A2/DI
A3
CS
RST
STNBY
SP
BUSWD
TEST
TPC1
TPC2
TOSEL1
TOSEL2
TIN
CLK16
DATA
FCK
BCK
FLOCK
BLOCK
CRC4
INT
DREQ
RDY
Function
Data bus I/O control 1 (SP=low)*1
Data bus I/O control 2 (SP=low)*1
DMA acknowledge (SP=low)*1
Write control signal (SP=low)*1
Read control signal (SP=low)*1
Address input
0 (SP=low) CCB CL input (SP=low)
1 (SP=low) CCB CE input (SP=low)
2 (SP=low) CCB DI input (SP=low)
3 (SP=low)*1
Chip select input (SP=L)*1
System reset input (negative logic)
Standby mode (positive logic)
SP=low: parallel, SP=high: serial
BUSWD=low: 8 bits, BUSWD=high: 16bits
The test pin must be connected to the digital system ground (VSS).
Must be connected to the digital system power supply (VDD) or ground
(VSS) in normal operation.
As above
As above
As above
As above
Clock regeneration monitor
Demodulated data monitor
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization
Outputs a high level during block synchronization
Level 4 CRC detection result output
External CPU interrupt request output
DMA request signal
Read ready signal
Output
Input
Input
I/O
Pin circuit
INT
D0 to D15
A0/CL
A1/CE
A2/DI
A3
DO
SP
BUSWD
TIN
FLOUT
VREF
CRC4
IOCNT1
IOCNT2
DREQ
DACK
CS
RD
WR
RDY
CIN
Continued on next page.
No.6870-5/29
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
