Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (BGA Only)
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Pin to Pin compatible to the higher density of IDT72V2103/72V2113
Big-Endian/Little-Endian user selectable byte representation
5V tolerant inputs
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (BGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
*Available on the
BGA package only.
D
0
-D
n
(x9 or x18)
WEN
WCLK/WR
*
INPUT REGISTER
LD SEN
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
*
ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 18 or 1,024 x 9
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
FLAG
LOGIC
READ POINTER
BE
IP
IW
OW
MRS
PRS
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
ASYR
*
RCLK/RD
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY SCAN)
*
OE
Q
0
-Q
n
(x9 or x18)
REN
*
4666 drw01
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2003
DSC-4666/12
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO)
memories with clocked read and write controls and a flexible Bus-Matching x9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
• Flexible x9/x18 Bus-Matching on both read and write ports
• The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
PIN CONFIGURATIONS
WCLK
PRS
MRS
LD
FWFT/SI
FF/IR
PAF
OW
FSEL0
HF
FSEL1
BE
IP
V
CC
PAE
PFM
EF/OR
RM
RCLK
REN
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
INDEX
WEN
SEN
DNC
(1)
V
CC
DNC
(1)
IW
GND
D17
V
CC
D16
D15
D14
D13
GND
D12
D11
D10
D9
D8
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RT
OE
V
CC
Q17
Q16
GND
GND
Q15
Q14
V
CC
Q13
Q12
GND
Q11
GND
Q10
V
CC
Q9
Q8
Q7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4666 drw02
NOTE:
1. DNC = Do Not Connect.
D7
D6
GND
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
GND
Q6
TQFP (PN80-1, order code: PF)
TOP VIEW
2
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS FIFO FIFO
8K xx18, 16K x 9/18, 2K x 9/18, 4K x 9/18, 8K 128K x 16K x256K x 9/18,9/18, 64K x 9/18, 128K x 9
512 18, 1K x 9/18, 32K x 9/18, 64K x 9/18, x 9/18, 9/18, 9/18, 32K x 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either an 18-bit or a 9-bit width as determined by the state
of external control pins Input Width (IW) and Output Width (OW) during the Master
Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when
WEN
is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN
input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when
REN
is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN
input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the
OE
input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
PIN CONFIGURATIONS (CONTINUED)
A1 BALL PAD CORNER
A
WCLK
PRS
MRS
SEN
LD
PAF
FSEL0
HF
BE
ASYR
PFM
PAE
RM
EF/OR
RT
REN
B
WEN
FWFT/SI
FF/IR
OW
FSEL1
IP
RCLK
OE
C
ASYW
V
CC
V
CC
V
CC
V
CC
V
CC
D
D17
IW
D15
V
CC
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
V
CC
Q16
Q14
Q17
Q15
E
D16
F
D13
D14
V
CC
GND
GND
GND
GND
GND
V
CC
Q13
Q12
G
D11
D12
V
CC
GND
GND
GND
V
CC
Q11
Q10
H
D8
D9
D10
V
CC
V
CC
V
CC
V
CC
Q1
Q9
Q8
J
D6
D7
D2
D0
TMS
TRST
TCK
TDO
Q2
Q4
Q7
Q6
K
D5
D4
D3
D1
TDI
Q0
Q3
Q5
1
2
3
4
5
6
7
8
9
10
4666 drw02b
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
TOP VIEW
3
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN
for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR
(Empty Flag or Output Ready),
FF/IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable
Almost-Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions are selected in IDT Standard mode. The
IR
and
OR
functions are
selected in FWFT mode.
HF, PAE
and
PAF
are always available for use,
irrespective of timing mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that
PAE
can be set to switch at a predefined number of locations
from the empty boundary and the
PAF
threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programming,
SEN
together with
LD
on each rising edge of WCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel from Q
n
regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing
before Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
PRS
is useful for resetting a device in mid-
operation, when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE
and
PAF
flags.
If asynchronous
PAE/PAF
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH on the LOW-
PARTIAL RESET (PRS)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
(x9 or x18) DATA IN (D0 - Dn)
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
IDT
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
OUTPUT ENABLE (OE)
(x9 or x18) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
4666 drw03
INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
TM
NARROW BUS FIFO FIFO
8K xx18, 16K x 9/18, 2K x 9/18, 4K x 9/18, 8K 128K x 16K x256K x 9/18,9/18, 64K x 9/18, 128K x 9
512 18, 1K x 9/18, 32K x 9/18, 64K x 9/18, x 9/18, 9/18, 9/18, 32K x 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
to-HIGH transition of WCLK. Similarly, the
PAF
is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF
configuration is selected , the
PAE
is asserted
and updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. The
mode desired is configured during master reset by the state of the Programmable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the
RT
input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the memory
array. A zero-latency retransmit timing mode can be selected using the
Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select
zero-latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmitted will be placed on the output register with respect to the same
RCLK edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for
Retransmit Timing
with normal latency. Refer
to Figure 13 and 14 for
Retransmit Timing
with zero-latency.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D
0
-D
n
) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D
8
during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected, then
D
8
is assumed to be a valid bit and D
16
and D
17
are ignored. IP mode is selected
during Master Reset by the state of the IP input pin. This mode is relevant only
when the input width is set to x18 mode. Interspersed Parity control only has
an effect during parallel programming of the offset registers. It does not effect the
data written to and read from the FIFO.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are fabricated using IDT’s high speed submicron CMOS technology.
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