CY7C1373BV25
CY7C1371BV25
512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture
Features
•
Pin-compatible and functionally equivalent to ZBT
devices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for Flow-Thru operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V +5% power supply
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
•
•
•
•
•
•
— 10 ns (for 83-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100-pin TQFP and 119-ball BGA packages
Burst Capability–linear or interleaved burst order
JTAG boundary scan for BGA packaging version
Automatic power-down available using ZZ mode or CE
deselect
Functional Description
The CY7C1371BV25 and CY7C1373BV25 are 2.5V, 512K×36
and 1M×18 Synchronous Flow-Thru Burst SRAMs, respec-
tively, designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1371BV25/CY7C1373BV25 is
equipped with the advanced No Bus Latency™ (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write/Read
transitions.The CY7C1371BV25/CY7C1373BV25 is pin-
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the Byte Write Selects
for
CY7C1371BV25
and
BWS
a,b
for
(BWS
a,b,c,d
CY7C1373BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
ZZ may be tied to LOW if it is not used.
Synchronous Chip Enable (CE
1
, CE
2
, CE
3
on the TQFP, CE
1
on the BGA) and an asynchronous Output Enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a write
sequence.
D
Data-In REG.
Q
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
AX
DQX
CY7C1371
X = 18:0
CY7C1373
X = 19:0
DQ
x
DP
x
X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
OE
Selection Guide
117 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
7.5
210
30
100 MHz
8.5
190
30
83 MHz
10.0
160
30
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05250 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1373BV25
CY7C1371BV25
Pin Definitions (100-Pin TQFP)
Pin Name
A0
A1
A
BWSa
BWSb
BWSc
BWSd
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the 266,144 address locations. Sampled at the
rising edge of the CLK.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb
controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input.
Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW.
Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Clock Enable Input, active LOW.
When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[x]
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE. DQ a,b,c and
d are 8 bits wide.
Bidirectional Data Parity I/O lines.
Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DPa is controlled by BWSa, DPb is controlled by
BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. DP a,b,c and d
are 1 bit wide
ZZ “sleep” Input.
This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Mode Input.
Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Power supply inputs to the core of the device.
Page 5 of 25
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQa
DQb
DQc
DQd
I/O-
Synchronous
DPa
DPb
DPc
DPd
ZZ
MODE
I/O-
Synchronous
Input-
Asynchronous
Input-pin
V
DD
Power Supply
Document #: 38-05250 Rev. *A
FPGA/CPLD
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