notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM
is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00
I
, 12/10/2012
1
IS49NLC93200,IS49NLC18160,IS49NLC36800
1 Package Ballout and Description
1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
VREF
VDD
VTT
A22
1
A21
2
A5
A8
BA2
NF
3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
2
VSS
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
A6
A9
NF
3
DK#
CS#
A16
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
ZQ
3
VEXT
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
A7
VSS
VDD
VDD
VSS
A17
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
VEXT
11
TMS
DNU
4
DNU
4
QK0
DNU
4
DNU
4
A1
A4
BA0
BA1
A14
A11
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
DQ*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
9
2
2
2
1
3
1
1
31
4
144
Notes:
NOTES:
1. Reserved for future use. This signal is not connected.
1) Reserved for future use. This may
2.Reserved for future use. This signal is internally
optionally be connected to GND.
of an address
connected and has parasitic characteristics
2) Reserved for future use. This signal is
input signal.
internally connected
is internally
parasitic
and has
3. No function. This signal
and has
connected
parasitic characteristics of
address input signal.
characteristics of an
a clock input signal. This may
optionally be connected to GND.
This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has
3) No function. This signal is internally
parasitic characteristics of a I/O. This may optionally be
connected and has parasitic characteristics
connected to GND. Note that if ODT is enabled, these
of a
are High-Z.
pins
clock input signal. This may optionally
be connected to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00
I
, 12/10/2012
2
IS49NLC93200,IS49NLC18160,IS49NLC36800
1.2 288Mb (16Mx18) Common I/O BGA Ball-out (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
VREF
VDD
VTT
A22
1
A21
2
A5
A8
BA2
NF
3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
2
VSS
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
A6
A9
NF
3
DK#
CS#
A16
DNU
4
DNU
4
QK1
DNU
4
DNU
4
ZQ
3
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSS
VDD
VDD
VSS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
11
TMS
DNU
4
DNU
4
QK0
DNU
4
DNU
4
A1
A4
BA0
BA1
A14
A11
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
TDO
12
TCK
VDD
VTT
VSS
A20
2
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
DQ*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
18
2
4
2
1
3
1
1
20
4
144
Notes:
NOTES:
1. Reserved for future use. This may optionally be
1) Reserved for future use. This may
connected to GND.
optionally be connected to GND.
2. Reserved for future use. This signal is internally
2) Reserved
has parasitic characteristics of an address
connected and
for future use. This signal is
internally connected and has parasitic
input signal.
3. No function. This signal
address input signal.
characteristics of an
is internally connected and has
parasitic characteristics of
be connected to
This may
This may optionally
a clock input signal.
GND.
optionally be connected to GND.
3) No function. This signal is internally
4. Do not use. This signal is internally connected and has
connected and has
of a I/O. This
characteristics
parasitic characteristics
parasitic
may optionally be
of a clock input
Note that
This may optionally
connected to GND.
signal.
if ODT is enabled, these
be connected to GND.
pins are High-Z.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00
I
, 12/10/2012
3
IS49NLC93200,IS49NLC18160,IS49NLC36800
1.3 288Mb (8Mx36) Common I/O BGA Ball-out (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
VREF
VDD
VTT
1
A22
2
A21
A5
A8
BA2
DK0
DK1
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
2
VSS
DQ8
DQ10
DQ12
DQ14
DQ16
A6
A9
DK0#
DK1#
CS#
A16
DQ24
DQ22
QK1
DQ20
DQ18
ZQ
3
VEXT
DQ9
DQ11
DQ13
DQ15
DQ17
A7
VSS
VDD
VDD
VSS
A17
DQ25
DQ23
QK1#
DQ21
DQ19
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ1
DQ3
QK0#
DQ5
DQ7
A2
VSS
VDD
VDD
VSS
A12
DQ35
DQ33
DQ31
DQ29
DQ27
VEXT
11
TMS
DQ0
DQ2
QK0
DQ4
DQ6
A1
A4
BA0
BA1
A14
A11
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
12
TCK
VDD
VTT
VSS
2
A20
QVLD
A0
A3
CK
CK#
A13
A10
2
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
DQ*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
36
4
4
2
1
3
1
1
0
4
144
Notes:
1. Reserved for future use. This may optionally be
connected to GND.
2. Reserved for future use. This signal is internally
connected and has parasitic characteristics of an address
input signal. This may optionally be connected to GND.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00
I
, 12/10/2012
4
IS49NLC93200,IS49NLC18160,IS49NLC36800
1.4 Ball Descriptions
Symbol
A*
BA*
CK, CK#
CS#
DQ*
Type
Input
Input
Input
Input
I/O
Description
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE
REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of
CK.
Bank address inputs: Selects to which internal bank a command is being applied to.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising
edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
Data input: The DQ signals form the data bus. During READ commands, the data is referenced to both
edges of QK*. During WRITE commands, the data is sampled at both edges of DK.
Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to
both edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17
are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18
devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the
device.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
IEEE 1149.1 clock input: This ball must be tied to V
SS
if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
Input reference voltage: Nominally V
DDQ
/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are
aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and
QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not
used.
Power supply: Nominally, 1.8V.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
Power supply: Nominally, 2.5V.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, V
DDQ
/2.
Reserved for future use: This signal is internally connected.
Reserved for future use: This signal is not connected and can be connected to ground.
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
No function: These balls can be connected to ground.
DK*, DK*#
Input
DM
TCK
TMS,TDI
WE#, REF#
V
REF
ZQ
Input
Input
Input
Input
Input
I/O
QK*, QK*#
Output
QVLD
TDO
V
DD
V
DDQ
V
EXT
V
SS
V
SSQ
V
TT
A21
A22
DNU
NF
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
-
-
-
-
Integrated Silicon Solution, Inc. – www.issi.com –
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