D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
NTGS4111P
Power MOSFET
−30
V,
−4.7
A, Single P−Channel, TSOP−6
Features
•
•
•
•
•
Leading
−30
V Trench Process for Low R
DS(on)
Low Profile Package Suitable for Portable Applications
Surface Mount TSOP−6 Package Saves Board Space
Improved Efficiency for Battery Applications
Pb−Free Package is Available
http://onsemi.com
V
(BR)DSS
−30
V
R
DS(on)
TYP
38 mW @
−10
V
68 mW @
−4.5
V
P−Channel
1 2 5 6
I
D
MAX
−4.7
A
Applications
•
Battery Management and Switching
•
Load Switching
•
Battery Protection
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Steady
State
t
≤
5s
Power Dissipation
(Note 1)
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
Pulsed Drain Current
Steady
State
t
≤
5s
Steady
State
T
A
= 25°C
T
A
= 85°C
T
A
= 25°C
tp = 10
ms
P
D
I
DM
T
J
,
T
STG
I
S
T
L
I
D
T
A
= 25°C
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
P
D
Symbol
V
DSS
V
GS
I
D
Value
−30
±20
−3.7
−2.7
−4.7
1.25
2.0
−2.6
−1.9
0.63
−15
−55
to
150
−1.7
260
W
A
°C
A
°C
TG
M
G
A
1
TSOP−6
CASE 318G
STYLE 1
W
Unit
V
V
A
3
4
MARKING DIAGRAM &
PIN ASSIGNMENT
Drain Drain Source
6 5 4
TG M
G
G
1 2 3
Drain Drain Gate
= Specific Device Code
= Date Code*
= Pb−Free Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
THERMAL RESISTANCE RATINGS
Rating
Junction−to−Ambient – Steady State (Note 1)
Junction−to−Ambient – t
≤
5 s (Note 1)
Junction−to−Ambient – Steady State (Note 2)
Symbol
R
qJA
R
qJA
R
qJA
Max
100
62.5
200
Unit
°C/W
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
Device
NTGS4111PT1
NTGS4111PT1G
Package
TSOP−6
Shipping
†
3000 / Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.006 in sq).
TSOP−6 3000 / Tape& Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2009
July, 2009
−
Rev. 3
1
Publication Order Number:
NTGS4111P/D
NTGS4111P
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
V
GS(TH)
V
GS(TH)
/T
J
R
DS(on)
g
FS
C
ISS
C
OSS
C
RSS
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
t
d(ON)
t
r
t
d(OFF)
t
f
t
d(ON)
t
r
t
d(OFF)
t
f
Characteristic
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
Symbol
V
DS
t
RR
t
a
t
b
Q
RR
V
GS
= 0 V
dI
S
/dt = 100 A/ms, I
S
=
−1.0
A
Test Condition
V
GS
= 0 V,
I
S
=
−1.0
A
T
J
= 25°C
T
J
= 125°C
Min
V
GS
=
−4.5
V, V
DD
=
−15
V,
I
D
=
−1.0
A, R
G
= 6.0
W
V
GS
=
−10
V, V
DD
=
−15
V,
I
D
=
−1.0
A, R
G
= 6.0
W
V
GS
=
−10
V, V
DD
=
−15
V,
I
D
=
−3.7
A
V
GS
=
−10
V, I
D
=
−3.7
A
V
GS
=
−4.5
V, I
D
=
−2.7
A
V
DS
=
−10
V, I
D
=
−3.7
A
CHARGES, CAPACITANCES AND GATE RESISTANCE
750
V
GS
= 0 V, f = 1.0 MHz,
V
DS
=
−15
V
140
105
15.25
0.8
2.6
3.4
ns
32
nC
pF
V
GS
= V
DS
, I
D
=
−250
mA
−1.0
5.0
38
68
6.0
60
110
S
−3.0
V
mV/°C
mW
V
(BR)DSS
V
(BR)DSS
/T
J
I
DSS
I
GSS
V
GS
= 0 V,
V
DS
=
−24
V
T
J
= 25°C
T
J
= 125°C
V
GS
= 0 V, I
D
=
−250
mA
−30
−17
−1.0
−100
±100
nA
V
mV/°C
mA
Symbol
Test Condition
Min
Typ
Max
Unit
V
DS
= 0 V, V
GS
=
±20
V
SWITCHING CHARACTERISTICS, VGS =
−10
V
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
9.0
9.0
38
22
17
18
85
45
ns
SWITCHING CHARACTERISTICS, VGS =
−4.5
V
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Typ
−0.76
−0.60
17
9.0
8.0
8.0
nC
40
ns
Max
−1.2
Unit
V
11
15
28
22
20
28
56
50
3. Pulse Test: pulse width
v
300
ms,
duty cycle
v
2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTGS4111P
TYPICAL PERFORMANCE CURVES
(T
J
= 25°C unless otherwise noted)
12
−I
D,
DRAIN CURRENT (AMPS)
11
10
9
8
7
6
5
4
3
2
1
0
0
0.4
0.8
1.2
T
J
= 25°C
1.6
2
2.4
2.8
3.2
−10V
−4.5
V
−4.2
V
−8
V
−6
V
−5.5
V
−5
V
−3.6
V
−3.4
V
−3.2
V
−3
V
3.6
4
−3.8
V
−4
V
−I
D,
DRAIN CURRENT (AMPS)
12
11
10
9
8
7
6
5
4
3
2
1
0
1
25°C
T
J
=
−55°C
1.5
2
2.5
3
3.5
4
4.5
−V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
5
100°C
V
DS
≥
−10
V
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
0.1
Figure 2. Transfer Characteristics
0.2
T
J
= 25°C
I
D
=
−3.7
A
T
J
= 25°C
V
GS
=
−4.5
V
0.05
V
GS
=
−10
V
0.1
0
2
3
4
5
6
7
8
9
10
0
2.0
3.0
−I
D,
DRAIN CURRENT (AMPS)
4.0
−V
GS,
GATE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
R
DS(on),
DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
100000
−I
DSS,
LEAKAGE CURRENT (nA)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
I
D
=
−3.7
A
V
GS
=
−10
V
V
GS
= 0 V
T
J
= 150°C
10000
1.0
1000
T
J
= 100°C
0.5
−50
−25
0
25
50
75
100
125
150
100
5
15
10
20
25
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
30
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
NTGS4111P
TYPICAL PERFORMANCE CURVES
(T
J
= 25°C unless otherwise noted)
T
J
= 25°C
−V
GS,
GATE−TO−SOURCE VOLTAGE (VOLTS)
1400
C
iss
1300
1200 C
rss
1100
1000
900
800
700
600
500
400
300
C
oss
200
100
V
DS
= 0 V V
GS
= 0 V
C
rss
0
10
0
10
5
5
15
−V
GS
−V
DS
12
10
8
6
4
2
0
Q
GS
Q
GD
I
D
=
−3.7
A
T
J
= 25°C
V
DS
QT
V
GS
10
20
−V
DS,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
C
iss
20
25
30
0
1
2
0
3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q
g
, TOTAL GATE CHARGE (nC)
−GATE−TO−SOURCE
OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
100
−I
S
, SOURCE CURRENT (AMPS)
−I
D, DRAIN CURRENT (AMPS)
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
10
V
GS
= 0 V
T
J
= 150°C
10
100
ms
1 ms
V
GS
=
−20
V
SINGLE PULSE
T
C
= 25°C
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 ms
1
1
T
J
= 100°C
T
J
= 25°C
T
J
=
−55°C
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
−V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.1
dc
100
0.01
0.1
10
1
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.1
0.3
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
R
thja(t)
, EFFECTIVE TRANSIENT THERMAL RESPONSE
1
Figure 10. Diode Forward Voltage vs. Current
D = 0.5
0.2
0.1
0.05
0.02
0.1
0.01
0.01
0.001
Single Pulse
1E−06
1E−05
1E−04
1E−03
1E−02
t, TIME (s)
1E−01
1E+00
1E+01
1E+02
1E+03
0.0001
1E−07
Figure 11. FET Thermal Response
http://onsemi.com
4
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
