CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,
8192 x 9 and 16384 x 9
Integrated Device Technology, Inc.
IDT7203
IDT7204
IDT7205
IDT7206
FEATURES:
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
2048 x 9 organization (IDT7203)
4096 x 9 organization (IDT7204)
8192 x 9 organization (IDT7205)
16384 x 9 organization (IDT7206)
High-speed: 12ns access time
Low power consumption
— Active: 770mW (max.)
— Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
Pin and functionally compatible with IDT720X family
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing for #5962-88669 (IDT7203),
5962-89567 (IDT7203), and 5962-89568 (IDT7204) are
listed on this function
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7203/7204/7205/7206 are dual-port memory buff-
ers with internal pointers that load and empty data on a first-
in/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of
the Write ( ) and Read ( ) pins.
The devices 9-bit width provides a bit for a control or parity
at the user’s option. It also features a Retransmit ( ) capa-
bility that allows the read pointer to be reset to its initial position
when
is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT7203/7204/7205/7206 are fabricated using IDT’s
high-speed CMOS technology. They are designed for appli-
cations requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
W
R
•
•
•
•
•
•
•
•
RT
RT
•
.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
–D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
2048 x 9
4096 x 9
8192 x 9
16384 x 9
READ
POINTER
THREE-
STATE
BUFFERS
R
RS
READ
CONTROL
FLAG
LOGIC
DATA OUTPUTS
(Q
0
–Q
8
)
RESET
LOGIC
FL RT
EF
FF
/
XI
EXPANSION
LOGIC
XO HF
/
2661 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2661/9
5.04
1
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
3
Q
8
GND
NC
R
Q
4
Q
5
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P28-1
P28-2
D28-1
D28-3
SO28-3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
INDEX
D
2
D
1
D
0
XI
FF
Q
7
Q
6
Q
5
Q
4
R
2661 drw 02a
14
15
16
17
18
19
20
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
32
31
30
1
4
3
2
D
3
D
8
W
NC
Vcc
D
4
D
5
J32-1
&
L32-1
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL
/
RT
RS
EF
XO HF
/
Q
7
Q
6
2661 drw 02b
DIP
TOP VIEW
NOTES:
1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/
7205.
2. The small outline package SO28-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.
PLCC/LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal
Voltage with
Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to + 7.0
Military
–0.5 to +7.0
Unit
V
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CCM
V
CCC
GND
V
IH
(1)
V
IH
(1)
V
IL
(1)
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial and
Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to + 125
50
–55 to +125
–65 to +135
–65 to +155
50
°
C
°
C
°
C
mA
NOTE:
2661 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2661 tbl 02
5.04
2
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: V
CC
= 5.0V±10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V±10%, T
A
= –55°C to +125°C)
IDT7203/7204
Commercial
t
A
= 12, 15, 20, 25, 35, 50 ns
Symbol
I
LI(2)
I
LO(3)
V
OH
V
OL
I
CC1(4)
I
CC2(4)
I
CC3
(L)
(4)
(4)
IDT7203/7204
Military
(1)
t
A
= 20, 30, 40, 50, 65, 80, 120 ns
Min.
–1
–10
2.4
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
1
10
—
0.4
150
4
12
(5)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OH
= –2mA
Output Logic “0” Voltage I
OL
= 8mA
Active Power Supply Current
Standby Current (
R
=
W
=
RS
=
FL
/
RT
=V
IH
)
Power Down Current (All Input = V
CC
- 0.2V)
Power Down Current (All Input = V
CC
- 0.2V)
Min.
–1
–10
2.4
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
1
10
—
0.4
120
2
8
(5)
Unit
µA
µA
V
V
mA
mA
mA
mA
2661 tbl 03
12
25
I
CC3
(S)
NOTES:
1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3. R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. I
CC
measurements are made with outputs open (only capacitive loading).
5. Tested at f = 20MHz.
DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206
(Commercial: V
CC
= 5.0V±10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V±10%, T
A
= –55°C to +125°C)
IDT7205/7206
Commercial
t
A
= 15, 20, 25, 35, 50 ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3)
I
CC2(3)
I
CC3
(L)
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OH
= –2mA
Output Logic “0” Voltage I
OL
= 8mA
Active Power Supply Current
Standby Current (
R
=
W
=
RS
=
FL
/
RT
=V
IH
)
Power Down Current (All Input = V
CC
- 0.2V)
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
—
—
—
Max.
1
10
—
0.4
120
(4)
12
8
Min.
–1
–10
2.4
—
—
—
—
IDT7205/7206
Military
t
A
= 20, 30, 50 ns
Typ.
—
—
—
—
—
—
—
Max.
1
10
—
0.4
150
(4)
25
12
Unit
µA
µA
V
V
mA
mA
mA
2661 tbl 04
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2. R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3. I
CC
measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.04
3
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commercial
7203S/L12
7204S/L12
7203S/L15
7204S/L15
7205L15
7206L15
—
25
—
10
15
5
5
5
—
25
15
10
11
0
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
40
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
Com'l & Mil.
7203S/L20
7204S/L20
7205L20
7206L20
Max.
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
—
30
—
10
20
5
5
5
—
30
20
10
12
0
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
Com'l
7203S/L25
7204S/L25
7205L25
7206L25
—
35
—
10
25
5
5
5
—
35
25
10
15
0
35
25
25
10
35
25
25
10
—
—
—
—
—
25
—
—
—
—
25
—
—
25
10
10
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
35
35
35
25
25
—
25
25
35
35
—
25
25
—
—
—
Military
Com'l
7203S/L30 7203S/L35
7204S/L30 7204S/L35
7205L30
7205L35
7206L30
7206L35
—
40
—
10
30
5
5
5
—
40
30
10
18
0
40
30
30
10
40
30
30
10
—
—
—
—
—
30
—
—
—
—
30
—
—
30
10
10
25
—
30
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
30
30
—
30
30
40
40
—
30
30
—
—
—
—
45
—
10
35
5
10
5
—
45
35
10
18
0
45
35
35
10
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
—
—
35
10
15
22.2 MHz
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
45
45
45
30
30
—
30
30
45
45
—
35
35
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2661 tbl 05
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RTR
t
RTC
t
RT
t
RTS
t
RSR
t
EFL
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameters
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(2)
Read LOW to Data Bus LOW
(3)
Write HIGH to Data Bus Low-Z
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z
(3)
Write Cycle Time
Write Pulse Width
(2)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(2)
Reset Set-up Time
(3)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(2)
Retransmit Set-up Time
(3)
Retransmit Recovery Time
Reset to
EF
LOW
Retransmit LOW to Flags Valid
Read LOW to
EF
LOW
Read HIGH to
FF
HIGH
Read Pulse Width after
EF
HIGH
Write HIGH to
EF
HIGH
Write LOW to
FF
LOW
Write LOW to
HF
Flag LOW
Read HIGH to
HF
Flag HIGH
Write Pulse Width after
FF
HIGH
Read/Write LOW to
XO
LOW
Read/Write HIGH to
XO
HIGH
XI
XI
XI
Min. Max. Min. Max. Min.
—
20
—
8
12
3
3
5
—
20
12
8
9
0
20
12
12
8
20
12
12
8
—
—
—
—
—
12
—
—
—
—
12
—
—
12
8
8
(3, 4)
Min. Max. Min. Max. Min. Max. Unit
50
—
12
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
12
17
20
12
14
—
12
14
17
17
—
12
12
—
—
—
t
HFH
, t
FFH
Reset to
HF
and
FF
HIGH
Pulse Width
(2)
Recovery Time
Set-up Time
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.04
4
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Military
7203S/L40
7204S/L40
Com'l & Mil.
7203S/L50
7204S/L50
7205L50
7206L50
Min.
—
65
—
15
50
10
15
5
—
65
50
15
30
5
65
50
50
15
65
50
50
15
—
—
—
—
—
50
—
—
—
—
50
—
—
50
10
15
15
—
50
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
65
65
65
45
45
—
45
45
65
65
—
50
50
—
—
—
7203S/L65
7204S/L65
Military
(2)
7203S/L80
7204S/L80
7203S/L120
7204S/L120
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RSR
t
EFL
t
HFH
, t
FFH
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameters
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(3)
Min.
—
50
—
10
40
5
10
5
(4)
Max.
20
—
40
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
50
50
50
35
35
—
35
35
50
50
—
40
40
—
—
—
Max. Min.
—
80
—
15
65
10
15
5
—
80
65
15
30
10
80
65
65
15
80
65
65
15
—
—
—
—
—
65
—
—
—
—
65
—
—
65
10
15
Max. Min.
12.5
—
65
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
80
80
80
60
60
—
60
60
80
80
—
65
65
—
—
—
—
100
—
20
80
10
20
5
—
100
80
20
40
10
100
80
80
20
100
80
80
20
—
—
—
—
—
80
—
—
—
—
80
—
—
80
10
15
Max. Min.
10
—
80
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
100
60
60
—
60
60
100
100
—
80
80
—
—
—
—
140
—
20
120
10
20
5
—
140
120
20
40
10
140
120
120
20
140
120
120
20
—
—
—
—
—
120
—
—
—
—
120
—
—
120
10
15
Max.
7
—
120
—
—
—
—
—
35
—
—
—
—
—
—
—
—
—
—
—
—
—
140
140
140
60
60
—
60
60
140
140
—
120
120
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2661 tbl 06
Read LOW to Data Bus LOW
(4)
Write HIGH to Data Bus Low-Z
(4, 5)
Data Valid from Read HIGH
Read HIGH to Data Bus High-Z
Write Cycle Time
Write Pulse Width
(3)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(3)
Reset Set-up Time
(4)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(3)
Retransmit Set-up Time
(4)
Retransmit Recovery Time
Reset to
EF
LOW
Reset to
HF
and
FF
HIGH
Retransmit LOW to Flags Valid
Read LOW to
EF
Flag LOW
Read HIGH to
FF
HIGH
Read Pulse Width after
EF
HIGH
Write HIGH to
EF
HIGH
Write LOW to
FF
LOW
Write LOW to
HF
LOW
Read HIGH to
HF
HIGH
Write Pulse Width after
FF
HIGH
Read/Write LOW to
XO
LOW
Read/Write HIGH to
XO
HIGH
XI
XI
XI
—
50
40
10
20
0
50
40
40
10
50
40
40
10
—
—
—
—
—
40
—
—
—
—
40
—
—
40
10
15
Pulse Width
(3)
Recovery Time
Set-up Time
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5.04
5
ARM技术
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