5504 DCR
Direct Conversion Receiver
Advanced Information
April 2000
DESCRIPTION
The 5504 is a low cost, high performance direct
conversion receiver (DCR) specifically designed for
digital wireless applications. The DCR architecture
provides a receiver design with fewer external
components than the conventional dual conversion
approach. The 5504 is designed to operate over an
input frequency range of 950 to 2150 MHz. The
device accepts an input signal in this frequency
range and down converts directly to baseband. The
local oscillator signal is generated by a completely
integrated phase lock loop that is fully
programmable through a standard serial port
interface.
FEATURES
•
Wideband I/Q demodulator
– RF input 950 to 2150 MHz
– External lowpass filter
- Integrated post-filter baseband drivers
•
Integrated VCO and frequency synthesizer
•
AGC Amplifier
APPLICATIONS
•
Digital Satellite
•
VSAT Receivers
BLOCK DIAGRAM
VPA3a
VPA3b
VPA5a
VPA5b
VPD1
VPD2
VPA1
VPA6
VPA4
QO1
TP1
TP2
IO1
Qin
AGC
RFp
RFn
Dclk
Din
XTLP
XTLN
FILN
EON
Charge
Pump
Divide
11-bit
2
16
.............
2
6
Div
32/33
Serial
Port
Xtal
Osc.
C1
Iin
IO2
Power
Splitter
0
90
QO2
R3 R2 R1 R0
VCO1
VCO0
Divide
10-bit
C0
2
5 .............
2
0
Phase
Detect
Modulo
6-bit
VCO
RSHP
RSHN
RSLP
RSLN
Rext
VNS
VNA3b
VNA6a
VNA3a
VNA6b
1
VND1
VNA1
VNA4
VNA5
5504 DCR
Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
+5
AGC Amplifier
The 5504 RF input can be driven differentially or
single ended. The
RFp
and
RFn
inputs are self-
biasing and are designed to be driven from a 50
Ohm source. For single-ended operation, the
RFn
pin should be AC coupled to analog ground. A gain
control input, AGC, provides a 25 dB gain variation
with 0V providing minimum gain and 4V providing
maximum gain.
I/Q Mixer
The AGC amplifier drives the RF port of two identical
double balanced mixers. The LO ports of these
mixers are driven from an on-chip quadrature
network.
Low Pass Filtering and Buffering
Following each mixer, a buffer amplifier is provided
for driving an external passive low-pass filter. The
nominal output impedance for IO1 and Q01 is 50
ohms. A second high impedance buffer amplifier is
provided (IIN or
QIN)
for additional gain and isolation
after the filter. The figure below shows a typical filter
designed for 20 Megasymbol per second operation:
Note: A separate resonator circuit is required for
each oscillator
PLL Synthesizer
The synthesizer derives its reference from a source
which can be either an externally derived clock or an
external crystal coupled to the internal oscillator.
This source drives a programmable reference divider
with 15 preset divide ratios from 2 to 320. This
divider output provides the PLL reference by driving
one input of a phase/frequency detector. The VCO
output drives a divider chain incorporating a variable
modulus prescaler and divider. The divider is
programmed by a 17-bit control word. This divider
chain output drives the other input of the
phase/frequency detector.
Loop Filter
IIN/QIN
L2
Vtune
10 kΩ
12pF
BB835
L1
12pF
10 kΩ
C1
L2
47
Ω
L1
47
Ω
29
28
32
33
High
Low
5503
0.1 F
IO1/QO1
470nH
12pF
68pF
680nH
68pF
Dual VCO
The 5504 uses two VCOs to cover the entire
specified tuning range. Both VCOs use nearly
identical architecture with the only difference being
slight design modifications to optimize the range of
operation.
The lower range VCO requires an
external resonator that supports a tuning range of
950 to 1473 MHz. The higher range VCO requires a
similar resonator with inductor values designed to
support the range of 1390 to 2150 MHz. A typical
lumped-element resonator circuit incorporating
varactor tuning is shown in the following figure:
The phase/frequency detector interface consists of
two ports,
FILN
and
EON.
The
EON
drives the base
of an external NPN transistor, and the
FILN
provides
a feedback path for the loop filter elements. The
external transistor permits VCO tune voltages of
greater than 30V and also provides the final stage of
the loop amplifier. Below is shown a typical loop
filter:
+28V
1000pF
FILN
EON
10 k
Q1
10 kW
0.1 F
Vtune
2
5504 DCR
Direct Conversion Receiver
+5V
LOW PASS
FILTER
LOW PASS
FILTER
VPA3a
VPA1
VPA3b AGC VPA4 VPA5a VPA5b
42
11
4
5
30 31
IO1 QO1 QIN IIN
14 21 23 18
TP1C TP2C Rxt
43 44
24
17 IO2
7.68k
DEMOD/FEC
LNA
PIN
ATTEN.
15
VPD2 2
VPD1 3
RFP 7
RFN 6
AGC
AMP
ADC
QUAD
GEN
22 QO2
12
VNS
ADC
XTALP 46
XTAL
45 OSC
XTALN
47
SHIFT REGISTER/
DIN
48
RAM
DCLK
1
19
35
25
36
VND1 VNA1 VNA3a VNA3b RSLN
DUAL VCO
32
29 26
39 37
RSLP RSHN RSHP EON FILN
PLL
LOOP
FILTER
PLL SYNTH.
41 VNA4
9 VNA5b
8 VNA5a
LOW
HIGH
RESONATOR RESONATOR
DCR Application Drawing
3
5504 DCR
Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS
NAME
RFP, RFN
TYPE
I
DESCRIPTION
RF inputs: balanced differential inputs to the receiver. The input signals placed on this
line are amplified with a variable gain amplifier before being passed to the I/Q
demodulator.
Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input
amplifier gain from minimum to maximum. The gain increase is 25 dB typical
External loop filter interface.
Eon
drives the base of an external common emitter
transistor.
Filn
is the feedback input from the loop filter capacitor.
Reference crystal input.
An external crystal connected between these pins
establishes the reference frequency for the PLL synthesizer. Following this oscillator is
a programmable divider that establishes the synthesizer step size.
Baseband outputs.
These typically drive an A/D converter prior to digital
demodulation and processing.
I and Q channel outputs to external low pass filter. An external series resistor can be
connected between this output and the filter to provide the source match.
I and Q channel inputs from external low pass filter. These are high impedance inputs
(>5000Ω). The low pass filter must be designed for low input and high output
impedance.
External reference resistor. This resistor is connected to ground and must be 7.68k
±1%. It is used as a reference for internal bias currents.
High range VCO resonator inputs
Low range VCO resonator inputs
AGC
Eon, Filn
XTLP, XTLN
I
I/O
I
IO2, QO2
IO1, QO1
IIN, QIN
O
O
I
Rxt
RSHP, RSHN
RSLP, RSLN
DIGITAL PINS
Din
Dclk
I
I
I
I/O
I
I2C data. This signal is connected to the I2C internal block. An external resistor
(typically 2.2 k
Ω
) is connected between Din and Vcc for proper operation
I2C clock Input.
Dclk
should nominally be a square wave with a maximum frequency
of 400kHz. SCL is generated by the system I2C master.
4
5504 DCR
Direct Conversion Receiver
POWER PINS
VPA1, VPA3a,
VPA3b, VPA4,
VPA5a,
VPA5b, VPA6
VPD1, VPD2
VNA1, VNA3a,
VNA3b, VNA4,
VNA6, VNA7
VND1
VNS
I
Analog Vcc pins
I
I
Digital Vcc pin.
Analog ground pins.
I
I
Digital ground pin.
Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE
I C REGISTERS: WRITE MODE
2
S
address
0 A reg0
A
reg1
A reg2
A
reg3
5504 address
1
1
0
0
0
0
1
S: start bit
A: acknowledge bit
P: stop bit
TABLE 1: MICROCONTROLLER INTERFACE REGISTER
REGISTER
0
1
2
3
7(MSB)
0
2
7
6
2
14
6
16
5
2
13
5
15
4
2
2
x
test0
12
4
3
2
11
3
2
2
10
2
1
2
9
1
0 (LSB)
2
2
8
0
2
2
2
2
2
2
2
1
C1
R3
Pdisab
R2
vco1
R1
vco0
R0
x
C0
test1
5
传感器
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