SM572168U7UB6BU
June 8, 2000
Revision History
• June 8, 2000
Added Command Truth Table, Mode Register Table and notes.
Modified waveforms ( Auto Refresh (CBR) cycle and Power Down Mode and Clock Mask).
• March 19, 1998
Datasheet released.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SM572168U7UB6BU
June 8, 2000
128MByte (16M x 72) CMOS Synchronous DRAM Module - 8Mx8 based
200-pin DIMM, Buffered
Features
Standard
Configuration
Cycle Time
CAS# Latency
Burst Length
Burst Type
No. of Internal
Banks per SDRAM
• Operating Voltage
• Refresh
• Device Physicals
Functional Diagram
REGE
CKE0
CS0#
DQM
RAS#
CAS#
WE#
R
E
G
I
S
T
E
R
S
•
•
•
•
•
•
•
:
:
:
:
:
:
:
:
:
:
JEDEC
ECC
10/12/15ns
3&4
1, 2, 4, 8 or Page
Linear/Interleave
2/4
3.3V
4K/8K
400mil TSOP
• Lead Finish
• Length x Height
• No. of sides
:
:
:
Gold
6.051" x 1.250"
Double-sided
8Mx16
Block
8Mx16
Block
8Mx16
Block
8Mx16
Block
8Mx8
SDRAM
CKE1
CS1#
8Mx16
Block
8Mx16
Block
8Mx16
Block
8Mx16
Block
8Mx8
SDRAM
DQ0~DQ15
DQ16~DQ31
DQ32~DQ47
DQ48~DQ63
DQ64~DQ71
DQ0~DQ71
CLK0
PLL
Clock
Buffer
Feedback
CK0
CK10
CK1~CK9
(to SDRAM
devices 1~18)
Notes:
1. A0~A11 and BA0 to all SDRAMs through register.
2. A12/BA1 to all SDRAMs through register.
3. Register Block comprises of two registers.
4. This configuration permits QWORD Write only.
5. Data is terminated using 10Ω series resistors.
6. REGE, when asserted active high the buffer-register operates in Register mode,
when deasserted inactive low the buffer-register operates in “real-time” buffer mode.
7. Each 8Mx16 Block comprises of two 8Mx8 SDRAMs.
V
DD,
V
DDQ
V
SS
Decoupling capacitors
to all devices.
( All specifications of this device are subject to change without notice.)
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SM572168U7UB6BU
June 8, 2000
Pin Name
A0~A12
BA0, BA1
DQ0~DQ71
CLK0
RAS#
CAS#
CKE0, CKE1
IN, OUT
CS0#, CS1#
REGE
Column Addresses
Bank Select Address
Data Inputs/Outputs
Clock Inputs
Row Address Strobe
Column Address Strobe
Clock Enable
Physical Detect Input/Output
Chip Select Input
Register Enable
DQM
WE#
PDE#
PD1~PD8
ID1~ID3
V
DD
V
DDQ
V
SS
NC
Data Mask
Write Enable
PD Buffer Enable
Presence Detects
Identification Outputs
Power Supply
Power Supply
Ground
No Connection
Presence Detect Pins
Access Time
10ns 12ns 15ns
NC
NC
NC
NC
NC
NC
L
L
L
L
L
L
NC
L
NC
L
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
L=V
OL
Notes :
1. The unbuffered physical detect pins
IN and OUT are shorted together on
the DIMM.
2. Presence detect pins PD1~PD8 are
buffered and enabled by PDE#.
3. VDD and VDDQ are common
for this module.
4. A10/AP initiates auto
precharge.
5. BA1 is NC for 2 bankSDRAMs.
6. A12 is NC for 4 bank SDRAMs.
Addressing Scheme
2 Bank Devices
A0~A12 : Row Addresses
A0~A8
: Column Addresses
BA0
: Bank Select Address
4 Bank Devices
A0~A11 : Row Addresses
A0~A8
: Column Addresses
BA0, BA1 : Bank Select Addresses
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
Name
V
DD
NC
NC
IN
OUT
ID1
ID2
V
SS
DQ67
DQ66
V
DDQ
DQ65
DQ64
V
SS
DQ63
DQ62
NC
DQ61
DQ60
V
DDQ
NC
NC
V
SS
NC
NC
V
DDQ
DQ51
DQ50
V
SS
DQ49
DQ48
V
DDQ
DQ43
DQ42
V
SS
DQ41
DQ40
V
DDQ
A4
A5
Pin Pin
No. Name
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V
SS
A8
A9
V
DD
CKE1
CKE0
V
SS
CAS#
NC
V
DD
V
SS
RAS#
V
SS
A12 ( Note 6)
A11
V
DD
A0
A1
V
SS
DQ35
DQ34
V
DDQ
DQ33
DQ32
V
SS
DQ27
DQ26
V
DDQ
DQ25
DQ24
V
SS
DQ19
DQ18
V
DDQ
DQ17
DQ16
V
SS
NC
NC
V
DDQ
Pin
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin
Name
DQ15
DQ14
V
SS
DQ13
DQ12
V
DDQ
DQ7
DQ6
V
SS
DQ5
DQ4
V
DDQ
PDE#
PD1
PD2
PD3
PD4
NC
NC
V
SS
NC
NC
V
SS
REGE
NC
NC
ID3
DQ71
DQ70
V
SS
DQ69
DQ68
V
DDQ
NC
V
SS
NC
DQ59
DQ58
V
SS
DQ57
Pin Pin
No. Name
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DQ56
V
DDQ
DQ55
DQ54
V
SS
DQ53
DQ52
V
DDQ
DQ47
DQ46
V
SS
DQ45
DQ44
V
DDQ
DQ39
DQ38
V
SS
DQ37
DQ36
V
DD
A6
A7
V
SS
BA0
NC
V
DD
DQM
WE#
V
SS
NC
CLK0
V
DD
CS1#
CS0#
V
SS
BA1 (Note 5)
A10/AP
V
DD
A2
A3
Pin Pin
No. Name
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
V
SS
DQ31
DQ30
V
DDQ
DQ29
DQ28
V
SS
DQ23
DQ22
V
DDQ
DQ21
DQ20
V
SS
NC
NC
V
DDQ
NC
V
SS
V
SS
NC
NC
V
DDQ
DQ11
DQ10
V
SS
DQ9
DQ8
V
DDQ
DQ3
DQ2
V
SS
DQ1
DQ0
PD5
PD6
PD7
PD8
V
DD
NC
NC
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID1
ID2
ID3
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SM572168U7UB6BU
June 8, 2000
DC Characteristics
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperature
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
- 0.5 to +4.6
18
0 to +70
- 55 to +125
50
Unit
V
W
°C
°C
mA
Recommended DC Operating Conditions
(T
A
= 0 to +70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.5
0.8
Unit
V
V
V
V
Capacitance
(V
CC
= 3.3V±0.3V, T
A
= +25°C)
Parameter
Input Capacitance (All signals except Data)
Input/Output Capacitance (DQ0~DQ71)
Notes : Capacitance is sampled per Mil-Std-883.
Symbol
C
I1
C
I/O
Max
18
24
Unit
pF
pF
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SM572168U7UB6BU
June 8, 2000
DC Characteristics (cont’d)
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70 °C)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
I
LI
I
LO
V
OH
V
OL
Test Conditions
0V
≤
V
in
≤
V
CC
+0.3V
0V
≤V
out
≤
V
CC
D
out
= Disable
High I
out
= -2mA
Low I
out
= 2mA
2.4
-
-
0.4
2.4
-
-
0.4
2.4
-
-
0.4
V
V
10ns
12ns
Min Max Min Max
-10
10
-10
10
-20
20
-20
20
15ns
Min Max
-10
10
-20
20
Unit
µA
µA
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70
°C)
Parameter
Operating Current
Symbol
I
CC1
Test Conditions
Burst Length = 1, t
CLK
= min.
All Banks Active
CKE =V
IL
, t
CLK
= min.
All Banks Idle
CKE =V
IH
, t
CLK
= min.
All Banks Idle
CKE =V
IL
, t
CLK
= min.
Any Bank Active
CKE =V
IH
, t
CLK
= min.
Any Bank Active
t
CLK
= min.
t
CLK
= min., t
RC
= min.
Auto Refresh
CKE =V
IL
10ns
1513
82
388
118
478
1603
1870
64
Max.
12ns
1423
82
388
118
478
1423
1738
64
Unit
15ns
1333
82
388
118
478
1153
1603
64
mA
mA
mA
mA
mA
mA
mA
mA
Note
1, 2, 3
1, 2, 3
1, 2 , 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Precharge Standby Current
I
CC2
Active Standby Current
I
CC3
Burst Mode Current
Refresh Current
Self Refresh Current
I
CC4
I
CC5
I
CC6
Notes:
1.
2.
3.
I
CC
depends on output load condition when the device is selected. I
CC
(max) is specified at the output open condition.
An initial pulse of 200µs is required after power-up followed by a minimum of eight Auto-Refresh-Cycles.
All currents are for 4 bank, 4K refresh SDRAMs.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: +44-1908 234030 • Fax: +44-1908-234191
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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