Latch-Up Current.................................................... > 200 mA
83.3
9
12
5
5
4
0
9
140
150
7C441–14
7C443–14
71.4
10
14
6.5
6.5
5
0
10
140
150
7C441–20
7C443–20
50
15
20
9
9
6
0
15
120
130
7C441–30
7C443–30
33.3
20
30
12
12
7
0
20
100
110
Maximum Ratings
[1]
(Above which the useful life
may be impaired. For user guidelines, not test-
ed.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Pin Definitions
Signal Name
D
0–8
Q
0–8
ENW
ENR
CKW
CKR
F1
F2
MR
I/O
I
O
I
I
I
I
O
O
I
Description
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
0
– D
8
)
into the FIFO’s memory
Data Outputs: when the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
0
–
Q
8
) out of the FIFO’s memory
Enable Write: enables the CKW input
Enable Read: enables the CKR input
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and updates the Almost
Full flag state
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and updates the Almost
Empty and Empty flag states
Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in (see
Table 1)
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in (see
Table 1)
Master Reset: resets the device to an empty condition
Document #: 38-06032 Rev. *A
Page 2 of 15
CY7C441
CY7C443
Electrical Characteristics
Over the Operating Range
7C441–12
7C443–12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OS[2]
I
CC1[3]
I
CC2[4]
I
SB[5]
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Operating Current
Operating Current
Standby Current
V
CC
= Max.,
GND < V
I
< V
CC
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–90
140
150
70
80
30
30
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
140
150
70
80
30
30
7C441–14
7C443–14
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
120
130
70
80
30
30
7C441–20
7C443–20
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
100
110
70
80
30
30
7C441–30
7C443–30
2.4
0.4
V
CC
0.8
+10
V
V
V
V
Min. Max. Min. Max. Min. Max. Min. Max. Unit
µ
A
mA
mA
mA
mA
mA
mA
mA
Capacitance
[6]
Parameter
C
IN
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
Unit
pF
AC Test Loads and Waveform
[7,8]
R1 500Ω
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
R2
333Ω
3.0V
GND
≤
3 ns
C441-4
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
C441-5
2V
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Test no more than one output at a time and do not test any output for more than one second.
3. Input signals switch from 0V to 3V with a rise/fall time of 3 ns or less, clocks and clock enables switch at maximum frequency (f
MAX
), while data inputs switch
at f
MAX
/2. Outputs are unloaded.
4. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
5. All inputs signals are connected to V
CC
. All outputs are unloaded. Read and write clocks switch at maximum frequency (f
MAX
).
6. Tested initially and after any design or process changes that may affect these parameters.
7. C
L
= 30 pF for all AC parameters.
8. All AC measurements are referenced to 1.5V.
Document #: 38-06032 Rev. *A
Page 3 of 15
CY7C441
CY7C443
Switching Characteristics
Over the Operating Range
[9]
7C441–12
7C443–12
Parameter
t
CKW
t
CKR
t
CKH
t
CKL
t
A[10]
t
OH
t
FH
t
SD
t
HD
t
SEN
t
HEN
t
FD
t
SKEW1
t
PMR
t
SCMR
t
OHMR
t
MRR
t
MRF
t
AMR
[11]
7C441–14
7C443–14
Min.
14
14
6.5
6.5
Max.
7C441–20
7C443–20
Min.
20
20
9
9
Max.
7C441–30
7C443–30
Min.
30
30
12
12
Max.
Unit
ns
ns
ns
ns
20
0
0
7
0
7
0
ns
ns
ns
ns
ns
ns
ns
20
0
30
30
0
0
30
ns
ns
ns
ns
ns
ns
ns
30
30
ns
ns
Description
Write Clock Cycle
Read Clock Cycle
Clock HIGH
Clock LOW
Data Access Time
Previous Output Data Hold After Read HIGH
Previous Flag Hold After Read/Write HIGH
Data Set-Up
Data Hold
Enable Set-Up
Enable Hold
Flag Delay
Opposite Clock After Clock
Opposite Clock Before Clock
Master Reset Pulse Width (MR LOW)
Last Valid Clock LOW Set-Up to MR LOW
Data Hold From MR LOW
Master Reset Recovery (MR HIGH Set-Up to
First Enabled Write/Read)
MR HIGH to Flags Valid
MR HIGH to Data Outputs LOW
Min.
12
12
5
5
Max.
9
0
0
4
0
4
0
9
0
12
12
0
0
12
12
12
0
14
14
0
0
14
0
0
5
0
5
0
10
0
0
6
0
6
0
10
0
20
20
0
0
20
14
14
15
15
t
SKEW2[12]
20
20
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in the AC Test Loads and Waveforms
and capacitance as in Note 7, unless otherwise specified.
10. Access time includes all data outputs switching simultaneously.
11. t
SKEW1
is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of
flag update). If the opposite clock occurs less than t
SKEW1
after the clock, the decision of whether or not to include the opposite clock in the current clock
cycle is arbitrary.
Note:
The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags,
CKR is the opposite clock for the Almost Full flag. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Almost Full flag, CKR
is the clock for Empty and Almost Empty flags.
12. t
SKEW2
is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag
update). If the opposite clock occurs less than t
SKEW2
before the clock, the decision of whether or not to include the opposite clock in the current clock cycle
is arbitrary. See Note 11 for definition of clock and opposite clock.
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