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IS63LV1024L-12BI

产品描述128KX8 STANDARD SRAM, 12ns, PBGA36, 10 X 8 MM, MO-207, TFBGA-36
产品类别存储    存储   
文件大小261KB,共16页
制造商ABLIC
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IS63LV1024L-12BI概述

128KX8 STANDARD SRAM, 12ns, PBGA36, 10 X 8 MM, MO-207, TFBGA-36

IS63LV1024L-12BI规格参数

参数名称属性值
厂商名称ABLIC
零件包装代码DSBGA
包装说明TFBGA,
针数36
Reach Compliance Codeunknown
最长访问时间12 ns
JESD-30 代码R-PBGA-B36
长度10 mm
内存密度1048576 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端子数量36
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织128KX8
封装主体材料PLASTIC/EPOXY
封装代码TFBGA
封装形状RECTANGULAR
封装形式GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.45 V
最小供电电压 (Vsup)3.15 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式BALL
端子节距0.75 mm
端子位置BOTTOM
宽度8 mm
Base Number Matches1

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IS63LV1024
IS63LV1024L
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
• High-speed access times:
8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
• Lead-free Available
FEBRUARY 2010
DESCRIPTION
The
ISSI
IS63LV1024/IS63LV1024L is a very high-speed,
low power, 131,072-word by 8-bit CMOS static RAM in
revolutionary pinout. The IS63LV1024/IS63LV1024L is fab-
ricated using
ISSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low
power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024/IS63LV1024L operates from a single 3.3V
power supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K X 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. M
01/29/2010
1

 
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