CY8C28243, CY8C28403, CY8C28413
PRELIMINARY
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
®
PSoC Programmable System-on-Chip
❐
Features
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Varied Resource Options Within One PSoC Device Group
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds up to 24 MHz
❐
8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
3.0V to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.5V Using On-Chip Switched
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
Advanced Reconfigurable Peripherals (PSoC Blocks)
❐
Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 192 ksps with Sample and Hold
• Up to 4 Synchronized or Independent Delta-Sigma ADCs
for Advanced Applications
❐
Up to 4 Limited Type E Analog Blocks Provide:
• Dual Channel Capacitive Sensing Capability
• Comparators with Programmable DAC Reference
• Up to 10-bit Single-Slope ADCs
❐
Up to 12 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Shift Register, CRC, and PRS Modules
• Up to 3 Full-Duplex UARTs
• Up to 6 Half-Duplex UARTs
• Multiple Variable Data Length SPI™ Masters or Slaves
• Connectable to All GPIO
❐
Complex Peripherals by Combining Blocks
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Main Oscillator
❐
Optional 32.768 kHz Crystal for Precise On-Chip Clocks
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
Flexible On-Chip Memory
❐
16K Bytes Flash Program Storage 50,000 Erase/Write Cy-
cles
❐
1K Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP™)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Programmable Pin Configurations
❐
25 mA Sink, 10 mA Drive on All GPIO
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Analog Input on All GPIO
❐
30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on all GPIO
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Additional System Resources
2
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Up to 2 Hardware I C Resources
• Each Resource Implements Slave, Master, or Multi-Master
Modes
• Operation Between 0 and 400 kHz
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Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Flexible Internal Voltage References
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full Featured In-Circuit Emulator, and Programmer
❐
Full Speed Emulation
❐
Flexible and Functional Breakpoint Structure
❐
128K Trace Memory
■
System Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
1K
Interrupt
Controller
Global Analog Interconnect
Flash 16K
Sleep and
Watchdog
SROM
CPU Core (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
■
Analog
Input
Muxing
Digital
Clocks
2
MACs
4 Type 2
2 I
2
C
Decimators Blocks
POR and LVD
System Resets
■
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-48111 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 10, 2009
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PRELIMINARY
CY8C28xxx
PSoC Functional Overview
The PSoC family consists of many devices with On-Chip
Controllers. These devices are designed to replace multiple
traditional MCU based system components with one low cost
single chip programmable component. A PSoC device includes
configurable analog blocks, digital blocks, and interconnections.
This architecture enables the user to create customized
peripheral configurations to match the requirements of each
individual application. In addition, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
The CY8C28xxx group of PSoC devices described in this data
sheet have multiple resource configuration options available.
Therefore, not every resource mentioned in this data sheet is
available for each CY8C28xxx subgroup. The CY8C28x45
subgroup has a full feature set of all resources described. There
are six more segmented subgroups that allow designers to use
a device with only the resources and functionality necessary for
a specific application. See
Table 2
on page 6 to determine the
resources available for each CY8C28xxx subgroup. The same
information is also presented in more detail in the
Ordering Infor-
mation
section.
The architecture for this specific PSoC device family, as shown
in the
System Block Diagram
on page 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. The configurable global bus system allows all the
device resources to be combined into a complete custom
system. PSoC CY8C28xxx family devices have up to six I/O
ports that connect to the global digital and analog interconnects,
providing access to up to 12 digital blocks and up to 16 analog
blocks.
alone or combined with other blocks to create 8, 16, 24, and
32-bit peripherals, which are called user modules. The digital
blocks can be connected to any GPIO through a series of global
buses that can route any signal to any pin.
Figure 1. Digital System Block Diagram
[1]
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
8
8
Row Input
Configuration
8
Row 1
DBC10
DBC11
DCC12
4
DCC13
4
8
Row Output
Configuration
Row Input
Configuration
Row 2
DBC20
DBC21
DCC22
4
DCC23
4
Row Output
Configuration
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO). The M8C CPU core is a powerful
processor with speeds up to 24 MHz, providing a four MIPS 8-bit
Harvard architecture microcontroller.
Memory encompasses 16K bytes of Flash for program storage,
1K bytes of SRAM for data storage. The PSoC device incorpo-
rates flexible internal clock generators, including a 24 MHz
internal main oscillator (IMO) accurate to 2.5% over temperature
and voltage. A low power 32 kHz internal low speed oscillator
(ILO) is provided for the sleep timer and watch dog timer (WDT).
The 32.768 kHz external crystal oscillator (ECO) is available for
use as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL.
PSoC GPIOs provide connections to the CPU, and digital and
analog resources. Each pin’s drive mode may be selected from
8 options, which allows great flexibility in external interfacing.
Every pin also has the capability to generate a system interrupt
on high level, low level, and change from last read.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include:
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PWMs (8 to 16 bit, One-shot and Multi-shot capability)
PWMs with Dead band/Kill (8 to 16 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
Full-duplex 8-bit UARTs (up to 3) with selectable parity
Half-duplex 8-bit UARTs (up to 6) with selectable parity
Variable length SPI slave and master
❐
Up to 6 total slaves and masters (8-bit)
❐
Supports 8 to 16 bit operation
I
2
C slave, master, or multi-master (up to 2 available as System
Resources)
IrDA (up to 3)
Pseudo Random Sequence Generators (8 to 32 bit)
Cyclical Redundancy Checker/Generator (16 bit)
Shift Register (2 to 32 bit)
■
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■
The Digital System
The Digital System is composed of up to 12 configurable digital
PSoC blocks. Each block is an 8-bit resource that can be used
Note
1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.
Document Number: 001-48111 Rev. *D
Page 2 of 65
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PRELIMINARY
CY8C28xxx
The Analog System
The Analog System is composed of up to 16 configurable analog
blocks, each containing an opamp circuit that allows the creation
of complex analog signal flows. Some devices in this PSoC
family have an analog multiplex bus that can connect to every
GPIO pin. This bus can also connect to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing.
Some of the more common PSoC analog functions (most
available as user modules) are:
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Figure 2. Analog System Block Diagram for CY8C28x45 and
CY8C28x52 Devices
All GPIO
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[3]
P2[1]
Analog Mux
Bus
Analog-to-digital converters (6 to 14-bit resolution, up to 4,
selectable as Incremental or Delta Sigma)
Dedicated 10-bit SAR ADC with sample rates up to 192 ksps
Synchronized, simultaneous Delta Sigma ADCs (up to 4)
Filters (2 to 8 pole band-pass, low-pass, and notch)
Amplifiers (up to 4, with selectable gain to 48x)
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
Comparators (up to 6, with 16 selectable thresholds)
DACs (up to 4, with 6 to 9-bit resolution)
Multiplying DACs (up to 4, with 6 to 9-bit resolution)
High current output drivers (up to 4 with 30 mA drive)
1.3V reference (as a System Resource)
DTMF Dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
ACI4[1:0]
ACI5[1:0]
Block Array
ACC00
ASC10
ASD20
ACC01
ASD11
ASC21
ACC02
ASC12
ASD22
ACC03
ACE00
ACE01
ASD13
ASE10
ASE11
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *D
Page 3 of 65
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PRELIMINARY
CY8C28xxx
Figure 3. Analog System Block Diagram for CY8C28x43
Devices
All GPIO
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
Figure 4. Analog System Block Diagram for CY8C28x33
Devices
All GPIO
P0[7]
P0[4]
P0[5]
P0[2]
P0[0]
P2[6]
P0[3]
P0[6]
P0[4]
P0[1]
P2[3]
Analog Mux
Bus
P0[2]
P0[0]
AGNDIn RefIn
P2[6]
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
P2[1]
Analog Mux
Bus
P2[4]
Array Input Configuration
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI4[1:0]
ACI5[1:0]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
Block Array
ACC00
ASC10
ASD20
ACC01
ASD11
ASC21
ACC02
ASC12
ASD22
ACC03
ASD13
ASC23
ACC00
ASC10
ASD20
ACC01
ACE00
ACE01
ASD11
ASE10
ASE11
ASC21
Analog Reference
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *D
Page 4 of 65
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PRELIMINARY
CY8C28xxx
Figure 5. Analog System Block Diagram for CY8C28x23
Devices
P0[7]
P0[5]
Figure 6. Analog System Block Diagram for CY8C28x13
Devices
All GPIO
P0[7]
P0[3]
P0[4]
P0[1]
P2[3]
P2[1]
AGNDIn RefIn
P0[2]
P0[0]
P2[6]
Analog Mux
Bus
P0[6]
P0[6]
P0[4]
P0[2]
P0[0]
P0[5]
P0[3]
P0[1]
P2[4]
ACI0[1:0]
Array Input
Configuration
ACI1[1:0]
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACE00
ACE01
Block Array
ACC00
ASC10
ASD20
ACC01
ASD11
ASC21
ASE10
ASE11
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
Analog Reference
M8C Interface (Address Bus, Data Bus, Etc.)
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-48111 Rev. *D
Page 5 of 65
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