51
PRELIMINARY
CY7C008V/009V
CY7C018V/019V
3.3V 64K/128K x 8/9
Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15
[1]
/20/25 ns
• Low operating power
—
Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
µA
(typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
Logic Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
CE
L
CE
R
R/W
R
CE
0R
CE
1R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
A
0L
–A
15/16L
[3]
16/17
Address
Decode
16/17
True Dual-Ported
RAM Array
Address
Decode
16/17
16/17
A
0R
–A
15/16R
[3]
[3]
[3]
A
0L
–A
15/16L
CE
L
OE
L
R/W
L
SEM
L
[4]
Interrupt
Semaphore
Arbitration
A
0R
–A
15/16R
CE
R
OE
R
R/W
R
SEM
R
[4]
BUSY
L
INT
L
M/S
BUSY
R
INT
R
Notes:
1. Call for availability
2. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
3. A
0
–A
15
for 64K devices; A
0
–A
16
for 128K.
4. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 23, 1998
PRELIMINARY
Functional Description
The CY7C008V/009V and CY7018V/019V are low-power
CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitra-
tion schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous ac-
cess for reads and writes to any location in memory. The de-
vices can be utilized as standalone 8/9-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
CY7C008V/009V
CY7C018V/019V
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip select (CE) pin.
The CY7C008V/009V and CY7018V/019V are available in
100-pin Thin Quad Plastic Flatpacks (TQFP).
Pin Configurations
100-Pin TQFP
(Top View)
BUSYL
BUSYR
GND
INTR
INTL
A0R
A1R
A2R
A3R
A4R
A5R
A6R
M/S
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
[Note 5] A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
SEML
R/WL
OEL
GND
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R [Note 5]
GND
NC
NC
NC
NC
CE0R
CE1R
SEMR
R/WR
OER
GND
GND
NC
CY7C009V (128K x 8)
CY7C008V (64K x 8)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/01R
GND
NC
GND
VCC
GND
VCC
NC
NC
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Note:
5. This pin is NC for CY7C008V.
I/O0L
2
NC
PRELIMINARY
Pin Configurations
(continued)
100-Pin TQFP
(Top View)
BUSYL
BUSYL
INTR
GND
GND
INTL
VCC
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
M/S
NC
NC
CY7C008V/009V
CY7C018V/019V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
[Note 6] A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
SEML
R/WL
OEL
GND
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R [Note 6]
GND
NC
NC
NC
NC
CE0R
CE1R
SEMR
R/WR
OER
GND
GND
NC
CY7C019V (128K x 9)
CY7C018V (64K x 9)
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
GND
GND
VCC
GND
I/01R
VCC
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O1L
Selection Guide
CY7C008V/009V
CY7C018V/019V
-15
[1]
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for I
SB1
(mA) (Both ports
TTL level)
Typical Standby Current for I
SB3
(µA) (Both ports
CMOS level)
Shaded area contains advance information.
Note:
6. This pin is NC for CY7C018V.
I/O0L
I/O2L
CY7C008V/009V
CY7C018V/019V
-20
20
120
35
10
µA
NC
CY7C008V/009V
CY7C018V/019V
-25
25
115
30
10
µA
15
125
35
10
µA
3
PRELIMINARY
Pin Definitions
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
–A
16L
I/O
0L
–I/O
8L
SEM
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
R/W
R
OE
R
A
0R
–A
16R
I/O
0R
–I/O
8R
SEM
R
INT
R
BUSY
R
Right Port
CE
R
, CE
1R
Read/Write Enable
Output Enable
Description
CY7C008V/009V
CY7C018V/019V
Chip Enable (CE is LOW when CE
0
≤
V
IL
and CE
1
≥
V
IH
)
Address (A
0
–A
15
for 64K devices and A
0
–A
16
for 128K devices)
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices and I/O
0
–I/O
8
for x9)
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >1100V
Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied .............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Shaded area contains advance information.
4
PRELIMINARY
Electrical Characteristics
Over the Operating Range
CY7C008V/009V
CY7C018V/019V
-15
[1]
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Parameter
Output HIGH Voltage (V
CC
=3.3V, I
OH
=−4.0 mA)
Output LOW Voltage (I
OL
=4.0mA)
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current (V
CC
=Max,
I
OUT
=0 mA) Outputs Disabled
Com’l.
Indust.
35
80
10
75
50
120
100
105
-5
–10
125
2.2
0.8
5
10
185
-5
–10
120
140
35
45
75
85
10
10
70
80
Min
2.4
0.4
2.2
0.8
5
10
175
195
45
55
110
120
100
100
95
105
Typ
Max
Min
2.4
0.4
-20
Typ
Max
CY7C008V/009V
CY7C018V/019V
-25
Min
2.4
0.4
2.2
0.8
-5
–10
115
135
30
40
65
75
10
10
60
70
5
10
165
185
40
50
95
105
100
100
80
90
Typ
Max
Units
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
Standby Current (Both Ports TTL Lev- Com’l.
el) CE
L
& CE
R
≥
V
IH
, f=f
MAX
Indust.
Standby Current (One Port TTL Level) Com’l.
CE
L
| CE
R
≥
V
IH
, f=f
MAX
Indust.
Standby Current (Both Ports CMOS
Level) CE
L
& CE
R
≥
V
CC
−0.2V,
f=0
Standby Current (One Port CMOS
Level) CE
L
| CE
R
≥
V
IH
, f=f
MAX[7]
Com’l.
Indust.
Com’l.
Indust.
Shaded area contains advance information.
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
V
TH
= 1.4V
OUTPUT
C = 30pF
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
≤
3 ns
90%
90%
10%
≤
3 ns
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE,
& t
LZWE
including scope and jig)
Notes:
7. f
MAX
=1/t
RC
=All inputs cycling at f=1/t
RC
(except output enable). f=0 means no address or control lines change. This applies only to inputs at CMOS level standby
I
SB3
.
8. Tested initially and after any design or process changes that may affect these parameters.
5
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