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NTD5N50
Preferred Device
Power MOSFET
5 Amps, 500 Volts
N–Channel DPAK
Designed for high voltage, high speed switching applications in
power supplies, converters, power motor controls and bridge circuits.
Features
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•
•
•
•
•
•
•
•
•
•
•
Higher Current Rating
Lower RDS(on)
Lower Capacitances
Lower Total Gate Charge
Tighter VSD Specifications
Avalanche Energy Specified
Industry Standard DPAK Surface Mount Package
Switch Mode Power Supplies
PWM Motor Controls
Converters
Bridge Circuits
5 AMPERES
500 VOLTS
RDS(on) = 1700 mΩ
N–Channel
D
Typical Applications
G
S
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage
– Continuous
– Non–Repetitive (tp
v10
ms)
Drain – Continuous
– Continuous @ 100°C
– Single Pulse (tp
v10
µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C
when mounted with the minimum
recommended pad size
Operating and Storage Temperature
Range
Single Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL = 5 A, L = 10 mH, RG = 25
Ω)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient (Note 1.)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
500
500
"20
"40
5.0
3.4
18
96
0.77
1.75
Adc
4
Watts
W/°C
W/°C
1
TJ, Tstg
EAS
–55 to
150
125
°C
mJ
2 3
CASE 369
DPAK
(Straight Lead)
STYLE 2
Unit
Vdc
Vdc
Vdc
1 2
3
4
CASE 369A
DPAK
(Bent Lead)
STYLE 2
ORDERING INFORMATION
°C/W
R
θJC
R
θJA
R
θJA
TL
1.30
100
71.4
260
°C
Device
NTD5N50
NTD5N50–1
NTD5N50T4
Package
DPAK
DPAK
Straight Lead
DPAK
Shipping
75 Units/Rail
75 Units/Rail
2500 Tape & Reel
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 10 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2001
1
August, 2001 – Rev. 2
Publication Order Number:
NTD5N50/D
NTD5N50
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Collector Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±20
Vdc, VDS = 0)
ON CHARACTERISTICS
(Note 2.)
Gate Threshold Voltage
ID = 0.25 mA, VDS = VGS
Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 2.5 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 2.5 Adc)
(VGS = 10 Vdc, ID = 5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(VDS = 400 Vdc, ID = 5 Adc,
VGS = 10 Vdc)
(VDD = 250 Vdc, ID = 5 Adc,
VGS = 10 Vdc,
Vdc
RG = 9.1
Ω)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (Note 2.)
(IS = 5 Adc, VGS = 0 Vdc)
(IS = 5 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 5 Adc VGS = 0 Vdc,
Adc,
Vdc
diS/dt = 100 A/µs)
Reverse Recovery Stored
Charge
2. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
trr
ta
tb
QRR
VSD
–
–
–
–
–
–
0.9
0.8
415
100
315
1.8
1.0
–
–
–
–
–
µC
ns
Vdc
–
–
–
–
–
–
–
–
7.0
9.0
20
10
10
2.0
3.0
5.0
10
20
40
20
20
–
–
–
nC
ns
(VDS = 25 Vd VGS = 0 Vdc,
Vdc,
Vd
f = 1.0 MHz)
Ciss
Coss
Crss
–
–
–
520
170
11
730
240
20
pF
VGS(th)
2.0
–
RDS(on)
VDS(on)
–
–
gFS
2.0
–
–
4.0
10.2
8.9
–
mhos
–
2.7
6.4
1300
4.0
–
1700
Vdc
mV/°C
mΩ
Vdc
V(BR)DSS
500
–
IDSS
–
–
IGSS(f)
IGSS(r)
–
–
–
–
–
–
10
100
100
100
nAdc
–
590
–
–
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
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2
NTD5N50
10
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
8
6V
6
5V
8V
7V
5.5 V
ID, DRAIN CURRENT (AMPS)
9V
VGS = 10 V
10
VDS
≥
10 V
8
6
4
4.5 V
4
TJ = 25°C
2
2
TJ = 100°C
0
1
2
3
4
5
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
TJ = –55°C
4V
0
0
2
4
6
8
10
12 14
16
18
20 22 24
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
Figure 2. Transfer Characteristics
4
3.5
3
2.5
2
1.5
1
0.5
0
1
2
3
4
5
6
TJ = 25°C
VGS = 10 V
TJ = 100°C
3
TJ = 25°C
2.5
2
VGS = 10 V
1.5
VGS = 15 V
TJ = –55°C
1
2
3
4
5
6
7
8
9
10
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.5
2
100000
ID = 2.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
10000
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
1.5
TJ = 150°C
1
1000
0.5
TJ = 100°C
0
–50
–25
0
25
50
75
100
125
150
100
100
150
200
250
300
350
400
450
500
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
NTD5N50
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1200
1000
C, CAPACITANCE (pF)
Ciss
800
600
400
200
Crss
0
10
5
VGS
0
VDS
5
10
15
20
25
Crss
Coss
Ciss
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
VDS = 0 V
VGS = 0 V
TJ = 25°C
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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