HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7130SA/LA
IDT7140SA/LA
FEATURES
• High-speed access
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP
• Low-power operation
—IDT7130/IDT7140SA
—Active:
550mW (typ.)
—Standby:
5mW (typ.)
—IDT7130/IDT7140LA
—Active:
550mW (typ.)
—Standby:
1mW (typ.)
• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 Only)
•
BUSY
output flag on IDT7130;
BUSY
input on IDT7140
• Interrupt flags for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention (LA only)
• TTL-compatible, single 5V
±10%
power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-
Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
Both devices provide two independent ports with sepa-
rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance tech-
nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B, making it ideally suited to military tem-
perature applications demanding the highest level of per-
formance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
OE
R
R/
W
R
CE
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
10
(1,2)
A
9L
A
0L
MEMORY
ARRAY
Address
Decoder
A
9R
A
0R
10
NOTES:
1. IDT7130 (MASTER):
BUSY
is open
drain output and requires pullup
resistor of 270Ω.
IDT7140 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup
resistor of 270Ω.
CE
L
OE
L
R/
W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/
W
R
INT
L
(2)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INT
R
2689 drw 01
(2)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2689/7
6.01
1
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
R/
BUSY
L
R/
INT
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
OE
L
BUSY
R
INT
R
7 6
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
5 4
3 2
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
2689 drw 02
OE
R
1
52 51 50 49 48 47
46
45
44
43
R/
R/
W
L
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
IDT7130/
41
9
IDT7140
40
10
P48-1
39
&
11
C48-2
38
12
37
13
DIP
36
TOP
14
VIEW
(3)
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
CE
R
W
R
W
L
INT
L
CE
R
OE
L
CE
L
INT
R
V
CC
W
R
INDEX
N/C
N/C
A
0L
V
CC
BUSY
L
BUSY
R
CE
L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
2689 drw 04
IDT7130/40
J52-1
52-PIN PLCC
TOP VIEW
(3)
42
41
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O
7L
N/C
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
INT
R
BUSY
R
BUSY
L
BUSY
L
INT
L
INT
R
V
CC
V
CC
CE
R
BUSY
R
W
R
CE
L
W
L
W
R
W
L
INT
L
V
CC
CE
L
CE
R
OE
R
OE
L
A
0L
N/C
N/C
N/C
R/
R/
R/
INDEX
INDEX
6 5
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
7
8
9
10
11
12
13
14
15
16
17
4 3
2
1
48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R/
N/C
N/C
N/C
I/O
6R
I/O
4L
I/O
5L
I/O
6L
IDT7130/40
L48-1
&
F48-1
48-PIN LCC/ FLATPACK
TOP VIEW
(3)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
18
31
19 20 21 22 23 24 25 26 27 28 29 30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT7130/40
PP64-1 & PN64-1
64-PIN STQFP
64-PIN TQFP
TOP VIEW
(3)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.01
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
2689 drw 03
2689 drw 05
2
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
V
TERM
(2)
Terminal Voltage
with Respect to
GND
Operating
T
A
Temperature
Temperature
T
BIAS
Under Bias
Storage
T
STG
Temperature
I
OUT
DC Output
Current
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2689 tbl 02
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
2689 tbl 01
NOTES:
1. V
IL
(min.) > -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2689 tbl 03
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
7130SA
Symbol
|l
Ll
|
|l
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage
Current
(1)
Output Leakage
Current
(1)
Output Low Voltage
(l/O0-l/O
7
)
Open Drain Output
Low Voltage (
BUSY
,
INT
)
Output High Voltage
Test Conditions
V
CC
= 5.5V,
V
IN
= 0V to V
CCIN
= GND to V
CC
V
CC
= 5.5V,
CE
= V
IH
, V
OUT
= 0V to V
CC
C
l
OL
= 4mA
l
OL
= 16mA
l
OL
= 16mA
l
OH
= -4mA
7140SA
Min.
Max.
—
—
—
—
2.4
10
10
0.4
0.5
—
7130LA
7140LA
Max.
Max.
—
—
—
—
2.4
5
5
0.4
0.5
—
Unit
µA
µA
V
V
V
2689 tbl 04
NOTE:
1. At Vcc
<
2.0V leakages are undefined.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz) TQFP ONLY
(3)
Sy
mbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
IN
= 3dV
Max. Unit
9
pF
10
pF
2689 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V.
3. 11pF max. for other packages.
6.01
3
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1,6)
(V
CC
= 5.0V
±
10%)
7130X20
(2)
7130X25
(3)
7130X35 7130X55 7130X100
7140X25
(3)
7140X35 7140X55 7140X100
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
—
— 110 280
—
— 110 220
110 250 110 220
110 200 110 170
—
—
30
30
—
—
65
65
—
—
1.0
0.2
—
—
60
60
—
—
65
45
—
—
165
125
—
—
15
5
—
—
155
115
30
30
30
30
65
65
65
65
1.0
0.2
1.0
0.2
60
60
60
60
80
60
65
45
160
125
150
115
30
10
15
5
155
115
145
105
110 230
110 170
110 165
110 120
25
25
25
25
50
50
50
50
1.0
0.2
1.0
0.2
45
45
45
45
80
60
65
45
150
115
125
90
30
10
15
4
145
105
110
85
110
110
110
110
20
20
20
20
190
140
155
110
65
45
65
35
110
110
110
110
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
190
140
155
110
65
45
55
35
125
90
110
75
30
10
15
4
110
80
95
70
mA
Symbol
I
CC
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs
Full Standby Current
(One Port - All
CMOS Level Inputs)
Test Conditions
Version
SA
LA
COM'L. SA
LA
SA
LA
COM'L. SA
LA
MIL.
MIL.
MIL.
CE
L
and
CE
R
= V
IL
,
Outputs open,
f = f
MAX
(4)
I
SB1
CE
L
and
CE
R
= V
IH
,
f = f
MAX
(4)
mA
I
SB2
SA
LA
Active Port Outputs COM'L. SA
LA
Open, f = f
MAX
(4)
CE
"
A
"
=
V
IL
and
CE
"
B
"
=
V
IH
(7)
40 125
40 90
40 110
40 75
1.0
0.2
1.0
0.2
30
10
15
4
mA
I
SB3
CE
L
and
CE
R
> V
CC
-0.2V,
V
IN
> V
CC
-0.2V or
V
IN
< 0.2V,f = 0
(5)
SA
LA
COM'L. SA
LA
SA
LA
COM'L. SA
LA
MIL.
MIL.
mA
I
SB4
CE
"
A
"
<
0.2V and
CE
"
B
"
> V
CC
-0.2V
(7)
V
IN
> V
CC
-0.2V or
V
IN
< 0.2V,
Active Port Outputs
Open, f = f
MAX
(4)
40 110
40 85
40 100
40 70
mA
NOTES:
2689 tbl 06
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.
3. Not available in DIP packages.
4. At f = f
Max
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, T
A
=+25°C for Typ and is not production tested. Vcc
DC
= 100 mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DATA RETENTION CHARACTERISTICS
(LA Version Only)
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed but not production tested.
2689 tbl 07
Test Conditions
Mil.
Com’l.
lDT7130LA/IDT7140LA
Min.
Typ.
(1)
Max.
2.0
—
100
100
—
—
—
4000
1500
—
—
—
—
0
t
RC
(2)
Unit
V
µA
µA
ns
ns
V
CC
= 2.0V,
CE
> V
CC
-0.2V
V
IN
> V
CC
-0.2V or V
IN
< 0.2V
6.01
4
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
V
CC
4.5V
t
CDR
V
DR
≥
2.0V
4.5V
t
R
CE
V
DR
V
IH
V
IH
2692 drw 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1, 2, and 3
2689 tbl 08
5V
1250Ω
DATA
OUT
775Ω
30pF*
(*100pF for 55 and
100ns versions)
DATA
OUT
775Ω
5V
1250Ω
5pF*
Figure 1. Output Test Load
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* including scope and jig
5V
270Ω
BUSY
or
INT
30pF*
*
100pF for 55 and 100ns versions
2689 drw 07
Figure 3.
BUSY
and
INT
AC Output Test Load
6.01
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
