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PRELIMINARY
CY25403
CY25423
Three PLL Programmable Clock Generator
with Spread Spectrum
Features
• Three fully integrated phase-locked loops (PLLs)
• Input Frequency range:
— External crystal: 8 to 48 MHz
— External reference: 8 to 166 MHz clock
• Wide operating output frequency range
•
•
•
•
•
•
•
•
•
•
•
— 3 to 166 MHz
Programmable Spread Spectrum modulation frequency
range of 30 to 120 kHz with Lexmark profile
Center Spread: ±0.125% to ±2.5%
Down Spread: –0.25% to –5%
Frequency select feature with option to select four different
frequencies
Low-jitter, high-accuracy outputs
Up to three clock outputs
Programmable output drive strength
Glitch-free outputs while frequency switching
Four independent output voltages: 3.3V, 3.0V, 2.5V, and
1.8V
8-pin SOIC package
Commercial and Industrial temperature range
Benefits
• Multiple high-performance PLLs allow synthesis of
unrelated frequencies
• Nonvolatile programming for customized PLL frequencies,
spread spectrum characteristics, drive strength, crystal load
capacitance, and output frequencies
• Two Spread Spectrum capable PLLs with Lexmark profile
for maximum for EMI reduction
• Spread Spectrum PLLs can be disabled or enabled
separately
• PLLs can be programmed for system frequency margin
tests
• Meets critical timing requirements in complex system
designs
• Suitable for PC, consumer, and networking applications
• Ability to synthesize standard frequencies with ease
• Application compatibility in standard and low-power
systems
Block Diagram
3 of 4
Crossbar
Switch
OSC
PLL1
Output
Dividers
and
Drive
Strength
Control
CLK1
CLK2
CLK3
XIN
XOUT
FS0
FS1
SSON
MUX
and
Control
Logic
PLL2
(SS)
PLL3
(SS)
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12564 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 02, 2007
PRELIMINARY
CY25403
CY25423
Pin Configuration
XIN
VDD
CLK1
CLK2/FS0
1
2
3
4
8 LD SOIC
8
7
6
5
XOUT
GND
CLK3/SSON
PD#/OE/FS1
Pin Description - Memory Programmable 3-PLL device with 2 Spread Spectrum PLLs
Pin Number
1
2
3
4
5
6
7
8
XIN
VDD
CLK1
CLK2/FS0
PD#/OE/FS1
CLK3/SSON
GND
XOUT
Name
Input
Power
Output
Output/input
Input
Output/Input
Power
Output
I/O
Crystal or Clock Input
Power Supply
Programmable Clock Output
Programmable Clock Output or FS0
Power Down, Output Enable or FS1
Programmable Clock Output or SSON
Power Supply Ground
Crystal Output
for center spread is from ±0.125% to ±2.50%. The range for
down spread is from –0.25% to –5.0%. Contact the factory for
smaller or larger spread percentage amounts, if required.
The input to the CY25403 and CY25423 is either a crystal or
a clock signal. The input frequency range for crystals is 8 MHz
to 48 MHz, and for clock signals is 8 MHz to 166 MHz.
The CY25403 and CY25423 have up to three clock outputs
and each output has four possible input sources.There are two
frequency select lines FS(1:0) that provide an option to select
four different sets of frequencies among the each of the three
PLLs. Each output has programmable output divider options.
Output 1 has eight possible divider values and outputs 2–3
have four possible divider values for maximum flexibility. The
2 bit or 3 bit output dividers are programmable providing a wide
output frequency range.
The outputs are glitch-free when frequency is switched using
output dividers. The outputs have a predictable phase
relationship, if the clock source is the same PLL and divider
values are 2, 3, 4, or 6.
The CY25403 and CY25423 are 3-PLL memory program-
mable spread spectrum clock generators with three clock
outputs.
Table 1. Supply Voltage Options
Device
CY25403
CY25423
V
DD
Supply Voltage
2.5V, 3.0V or 3.3V
1.8V
Description
General Description
Th CY25403 and CY25423 are three PLL programmable
Spread Spectrum Clock Generators used to reduce EMI found
in high-speed digital electronic systems. Two of the three PLLs
have Spread Spectrum capability. The spread spectrum
feature are turned on or off using the control pin SSON.
The advantage of having three PLLs is that a single device can
generate up to three independent frequencies from a single
crystal or reference input frequency. Generally, a design
requires up to three oscillators to achieve the same result with
a single CY25403 or CY25423.
The device uses Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy significantly reduces the cost of complying with
regulatory agency (EMC) requirements and improves
time-to-market without degrading the system performance.
The CY25403 and CY25423 use a factory/field-programmable
configuration memory array to provide customization for
output frequencies, frequency select options, spread charac-
teristics like spread percentage and modulation frequency,
output drive strength and crystal load capacitance. A
customized device can be configured using Cyberclocks
TM
software or by contacting the factory.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range
Document #: 001-12564 Rev. *A
Page 2 of 8
PRELIMINARY
CY25403
CY25423
Absolute Maximum Conditions
Parameter
V
DD
V
IN
T
S
ESD
HBM
UL-94
MSL
Description
Supply Voltage
Input Voltage
Temperature, Storage
ESD Protection (Human
Body Model)
Flammability Rating
Moisture Sensitivity Level
Relative to V
SS
Non Functional
Condition
Min.
–0.5
–0.5
–65
2000
V-0
Max.
4.5
+150
Unit
V
°C
Volts
V
DD
+ 0.5 VDC
MIL-STD-883, Method 3015
@1/8 in.
SOIC package
–
1
Recommended Operating Conditions
Parameter
V
DD1
V
DD2
V
DD3
V
DD4
T
AC
T
AI
C
LOAD
t
PU
Operating Voltage, 3.3V
Operating Voltage, 3.0V
Operating Voltage, 2.5V
Operating Voltage, 1.8V
Commercial Ambient Temperature
Industrial Ambient Temperature
Max. Load Capacitance
Power-up time for all V
DD
pins to reach minimum specified voltage (power ramps must
be monotonic)
Description
Min.
3.0
2.7
2.25
1.65
0
–40
–
0.05
Typ.
–
–
–
–
–
–
–
–
Max. Unit
3.6
3.3
2.75
1.95
+70
+85
15
500
V
V
V
V
°C
°C
pF
ms
DC Electrical Specifications
Parameter
V
OL
V
OH
V
IL
V
IH
V
ILX
V
IHX
Description
Output Low Voltage, All CLK pins
Output High Voltage, All CLK pins
All Inputs except XIN
All Inputs except XIN
Input Low Voltage, clock input to XIN pin
Input High Voltage, clock input to XIN pin
Conditions
All V
DD
levels, I
OL
= 8 mA
All V
DD
levels, I
OH
= –8 mA
All V
DD
levels
All V
DD
levels
All V
DD
levels
All V
DD
levels
Min.
0
V
DD
– 0.4
–0.3
0.8 * V
DD
–0.3
1.44
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
0.4
V
DD
0.2 * V
DD
V
DD
+ 0.3
0.36
2.0
10
1
1
10
17
7
Unit
V
V
V
V
V
V
μA
μA
μA
μA
mA
pF
I
ILPDOE
I
IHPDOE
I
ILSR
I
IHSR
I
DD[1]
C
IN
Input Low Current, PD#/OE and FS0,1 pins V
IN
= V
SS
(Internal pull up = 100k typical)
Input High Current, PD#/OE and FS0,1 pins V
IN
= V
DD
(Internal pull up = 100k typical)
Input Low Current, SSON pin
Input High Current, SSON pin
Supply Current
Input Capacitance - All inputs except XIN
V
IN
= V
SS
(Internal pull down = 100k typical)
V
IN
= V
DD
(Internal pull down = 100k typical)
All clocks running, CL = 0
SSON, OE, PD# or FS inputs
Note
1. Configuration dependent.
Document #: 001-12564 Rev. *A
Page 3 of 8
PRELIMINARY
CY25403
CY25423
AC Electrical Specifications
Parameter
F
IN
(crystal)
F
IN
(clock)
F
OUT
DC
DC
Description
Crystal Frequency
Input Clock Frequency (XIN)
Output Clock Frequency
Conditions
Min.
8
8
3
45
Typ. Max. Unit
–
–
–
50
48
166
166
55
MHz
MHz
MHz
%
Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in
Figure 2;
t
1
/t
2
,
50% of V
DD
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
0.8
0.8
–
–
–
–
–
-
-
–
60
–
–
–
–
3
%
V/ns
V/ns
ps
ns
ms
E
R
E
F
T
CCJ1
T
LTJ
T
10
CLK1-3 Rising Edge Rate
CLK1-3 Falling Edge Rate
Cycle-to-cycle Jitter
Long Term Jitter
PLL Lock Time
V
DD
= All, 20% to 80% V
DD
V
DD
= All, 20% to 80% V
DD
Configuration dependent. See
Table 2
Configuration dependent. See
Table 2
Table 2. Configuration Example for Jitter
Reference
27MHz
27MHz
48 MHz
48 MHz
Description
T
CCJ1
T
LTJ
T
CCJ1
T
LTJ
Max Jitter (ps) on
Output 1(48MHz)
155
770
135
535
Max Jitter (ps) on Output 2
(27 MHz)
255
580
225
575
Max Jitter (ps) on
Output 3 (166 MHz)
170
630
100
520
Recommended Crystal Specification for SMD Package
Parameter
Fmin
Fmax
R1(max)
C0(max)
CL(max)
DL(max)
Minimum Frequency
Maximum Frequency
Maximum Motional Resistance (ESR)
Maximum Shunt Capacitance
Maximum Parallel Load Capacitance
Maximum Crystal Drive Level
Description
Range 1 Range 2 Range 3
8
14
135
4
18
300
14
28
50
4
14
300
28
48
30
2
12
300
Unit
MHz
MHz
Ω
pF
pF
μW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Fmin
Fmax
R1(max)
C0(max)
CL(max)
DL(max)
Minimum Frequency
Maximum Frequency
Maximum Motional Resistance (ESR)
MaximumShunt Capacitance
Maximum Parallel Load Capacitance
Maximum Crystal Drive Level
Description
Range 1 Range 2 Range 3
8
14
90
7
18
1000
14
24
50
7
12
1000
24
32
30
7
12
1000
Unit
MHz
MHz
Ω
pF
pF
μW
Document #: 001-12564 Rev. *A
Page 4 of 8
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