HIGH-SPEED 3.3V
8K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT70V25S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V25S
Active: 230mW (typ.)
Standby: 3.3mW (typ.)
— IDT70V25L
Active: 230mW (typ.)
Standby: 0.66mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V25 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
• Busy and Interrupt Flags
• Devices are capable of withstanding greater than 2001V
electrostatic charge.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, 84-pin PLCC, and 100-pin
TQFP
DESCRIPTION:
The IDT70V25 is a high-speed 8K x 16 Dual-Port Static
RAM. The IDT70V25 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
UB
R
R/
W
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L(1,2)
A
12L
A
0L
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
BUSY
R(1,2)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
INT
L(2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R (2)
M/
S
2944 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2944/3
6.39
1
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
Port RAM for 32-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 350mW of power.
The IDT70V25 is packaged in a ceramic 84-pin PGA, an
84-Pin PLCC and a 100-pin Thin Quad Plastic Flatpack.
PIN CONFIGURATIONS
(1,2)
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
V
CC
R/
L
SEM
L
INDEX
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
71
15
70
16
69
17
68
18
67
19
IDT70V25
66
20
J84-1
65
21
84-PIN PLCC
64
22
TOP VIEW(3)
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
OE
L
UB
L
LB
L
CE
L
W
BUSY
L
GND
M/
S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
R/
R
GND
A
12R
A
11R
SEM
R
I/O
9R
A
10R
A
9R
A
8R
A
7R
OE
R
UB
R
LB
R
CE
R
W
2944 drw 02
V
CC
R/
L
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
SEM
L
OE
L
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
73
72
71
70
69
68
67
UB
L
LB
L
CE
L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
66
65
64
63
62
61
60
59
58
57
56
55
54
53
W
INDEX
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
IDT70V25
PN100-1
100-PIN
TQFP
TOP VIEW(3)
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
R/
R
GND
UB
R
LB
R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
SEM
R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
CE
R
6.39
W
2944 drw 03
2
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D)
(1,2)
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
A
12L
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/
W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
INT
L
07
I/O
15L
75
I/O
14L
70
V
CC
74
BUSY
L
IDT7V025
G84-3
84-PIN PGA
TOP VIEW(3)
32
A
0L
31
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/
S
29
INT
R
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
0R
BUSY
R
27
26
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/
15
W
R
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
A
12R
H
A
10R
J
A
9R
K
A
7R
L
2944 drw 04
Index
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part- marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2944 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
12L
I/O
0L
– I/O
15L
CE
R
R/
W
R
OE
R
A
0R
– A
12R
I/O
0R
– I/O
15R
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
UB
R
LB
R
INT
R
BUSY
R
GND
6.39
3
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
X
L
L
L
L
L
L
X
NOTE:
R/
W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
Both Bytes Deselected
Mode
Deselected: Power Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
DATA
OUT
Read Lower Byte Only
High-Z
Outputs Disabled
2944 tbl 02
DATA
OUT
DATA
OUT
Read Both Bytes
1. A
0L
— A
12L
≠
A
0R
— A
12R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
Inputs
Outputs
CE
H
X
H
X
L
L
R/
W
H
H
OE
L
L
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
I/O
0-7
Mode
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
DATA
IN
DATA
IN
—
—
DATA
IN
DATA
IN
—
—
Write D
IN0
into Semaphore Flag
Write D
IN0
into Semaphore Flag
Not Allowed
Not Allowed
X
X
X
X
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
NOTE:
2944 tbl 03
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
- I/O
15
). These eight semaphores are addressed by A
0
- A
2
.
(1)
Commercial Unit
–0.5 to +4.6
V
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
–0.3
(1)
Typ.
3.3
0
—
—
Max. Unit
3.6
0
0.8
V
V
V
2944 tbl 06
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
°C
°C
°C
mA
Vcc+0.3 V
NOTES:
1. V
IL
≥
-1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
NOTES:
2944 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20 mA for the period over V
TERM
> Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
Max.
V
IN
= 3dV
V
OUT
= 3dV
9
10
Unit
pF
pF
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
3.3V
±
0.3
2944 tbl 05
NOTES:
2944 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.39
4
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 3.3V
±
0.3V)
IDT70V25S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
IDT70V25L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2944 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc
≤
2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 3.3V
±
0.3V)
70V25X25
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports — TTL
Level Inputs)
Standby Current
(One Port — TTL
Level Inputs)
Test
Condition
Version
COM’L. S
L
Typ.
(2)
80
80
Max.
170
120
70V25X35
Typ.
(2)
70
70
Max.
115
100
70V25X55
Typ.
(2)
Max. Unit
70
70
115
100
mA
f = f
MAX(3)
CE
= V
IL
, Outputs Open
SEM
= V
IH
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
CE
L
or
CE
R
= V
IH(5)
I
SB1
f = f
MAX(3)
COM’L. S
L
12
10
25
20
10
8
25
20
10
8
25
20
mA
I
SB2
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
COM’L. S
L
40
40
82
72
35
35
72
62
35
35
72
62
mA
I
SB3
Full Standby Current Both Ports
CE
L
and
(Both Ports — All
CE
R
≥
V
CC
- 0.2V
CMOS Level Inputs) V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V, f = 0
(4)
SEM
R
=
SEM
L
≥
V
CC
- 0.2V
Full Standby Current One Port
CE
L
or
(One Port — All
CE
R
≥
V
CC
- 0.2V
(5)
CMOS Level Inputs)
SEM
R
=
SEM
L
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V
Active Port Outputs Open,
f = f
MAX(3)
COM’L. S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
I
SB4
COM’L. S
L
50
50
81
71
45
45
71
61
45
45
71
61
mA
2683 tbl 09
NOTES:
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. Icc dc
=
70mA (typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t
RC
, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.39
5
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