• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
• Fast asynchronous address-to-data access time: 20ns
• User-controlled input pins included for bank selects
• Independent port controls with asynchronous address &
data busses
• Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
• Interrupt flags with programmable masking
• Dual Chip Enables allow for depth expansion without
external logic
•
UB
and
LB
are available for bus matching to x8 or x16
busses; also support very fast banking
• TTL-compatible, single 5V (±10%) power supply
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-
Switchable Dual-Ported SRAM organized into four indepen-
dent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Ac-
cesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(
CE
0
and CE
1
) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
R/
FUNCTIONAL BLOCK DIAGRAM
R/
L
0L
CE
1L
L
L
L
MUX
R
CONTROL
LOGIC
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
0R
CE
1R
R
R
R
I/O
8L-15L
I/O
0L-7L
I/O
CONTROL
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
8R-15R
I/O
0R-7R
A
13L
A
0L(1)
ADDRESS
DECODE
ADDRESS
DECODE
A
13R
A
0R(1)
BA
1L
BA
0L
BANK
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BANK
DECODE
BA
1R
BA
0R
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
A
5L(1)
A
0L(1)
L
/
L
L
MAILBOX
INTERRUPT
LOGIC
A
5R(1)
A
0R(1)
R
/
R
R
R/
L
L
L
L
R/
R
R
R
R
3592 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.29
2
I/O
9L
I/O
8L
Vcc
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O1
L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
Vcc
I/O
7R
I/O
8R
I/O
9R
NC
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CON'T.)
(1,2)
81
80
77
74
72
UB
R
69
MB
SEL
R
68
65
63
60
57
54
12
A
7R
84
A
8R
83
A
11R
78
BK
SEL
3
76
GND GND
67
64
NC
61
I/O
13R
I/O
10R
59
56
NC
53
73
LB
R
70
11
A
4R
87
A
5R
86
A
10R
82
A
13R
79
CE
1R
R/
W
R
71
CE
0R
GND I/O
14R
I/O
12R
I/O
9R
62
58
55
51
NC
50
75
66
OE
R
10
A
1R
90
A
2R
88
A
6R
85
A
9R
NC
I/O
15R
I/O
11R
NC
52
I/O
8R
49
I/O
7R
47
09
BA
0R
92
A
0R
91
A
3R
89
NC
48
Vcc
46
I/O
5R
45
08
BK
SEL
2
95
A
12R
94
BA
1R
93
INT
R
I/O
6R
44
I/O
4R
43
I/O
3R
42
07
GND
96
GND
97
IDT707288
G108-1
I/O
2R
39
I/O
1R
40
I/O
0R
41
98
06
INT
L
BK
SEL
1
100
NC
102
I/O
1L
108-Pin PGA
Top View
(3)
I/O
0L
37
GND
38
99
35
05
A
12L
101
BA
0L
103
A
0L
106
A
4L
1
4
8
12
17
21
25
I/O
4L
31
I/O
2L
34
GND
36
04
BA
1L
104
A
1L
105
Vcc
28
I/O
5L
32
I/O
3L
33
03
A
2L
107
2
A
3L
5
A
7L
7
A
10L
BK
SEL
0
10
UB
L
CE
1L
13
MB
SEL
L
GND
16
OE
L
I/O
14L
I/O
10L
19
22
NC
24
I/O
7
L
29
I/O
6L
30
02
A
5L
108
A
8L
3
6
A
11L
9
NC
GND I/O
13L
18
20
I/O
11L
23
26
NC
I/O
8L
27
11
LB
L
CE
0L
14
15
01
A
6L
A
A
9L
B
A
13L
C
Vcc
F
R/
W
L
G
NC
H
I/O
15L
J
I/O
12L
K
I/O
9L
L
NC
M
3592 drw 03
D
E
I NDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.29
3
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
ASSIGNING THE BANKS VIA THE EXTERNAL BANK
SELECTS
There are four bank select pins available on the IDT707288,
and each of these pins is associated with a specific bank within
the memory array. The pins are user-controlled inputs:
access to a specific bank is assigned to a particular port by
setting the input to the appropriate level. The process of
assigning the banks is detailed in Truth Table I. Once a bank
is assigned to a port, the owning port has full access to read
and write within that bank. The opposite port is unable to
access that bank until the user reassigns the port. Access by
a port to a bank which it does not control will have no effect if
written, and if read unknown values on D
0
-D
15
will be returned.
Each port can be assigned as many banks within the array as
needed, up to and including all four banks.
The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs are not tri-statable. When changing the bank
select inputs (changing the bank assignments), the device
must be write-disabled (
CE
and/or R/
W
set to V
IH
).
TRUTH TABLE I –
MEMORY BANK ASSIGNMENT
(
CE
AND/OR R/
W
= V
IH
)
(2,3)
BANK AND
BKSEL0
H
X
X
X
L
X
X
X
BKSEL1
X
H
X
X
X
L
X
X
BKSEL2
X
X
H
X
X
X
L
X
BKSEL3
X
X
X
H
X
X
X
L
DIRECTION
(1)
BANK 0 LEFT
BANK 1 LEFT
BANK 2 LEFT
BANK 3 LEFT
BANK 0 RIGHT
BANK 1 RIGHT
BANK 2 RIGHT
BANK 3 RIGHT
NOTES:
3592 tbl 02
1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second
16Kx16 memory spaces, Bank 2 to the third 16Kx16 memory spaces,
and Bank 3 to the fourth 16Kx16 memory spaces. 'LEFT' indicates the
bank is assigned to the left port; 'RIGHT' indicates the bank is assigned
to the right port.
2. The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs
are not tri-statable. When changing the bank select inputs (changing
the bank assignments), the device must be write-disabled (
CE
and/or
R/
W
set to V
IH
).
3. 'H' = V
IH
, 'L' = V
IL
, 'X' = Don't Care.
MAILBOX INTERRUPTS AND INTERRUPT CONTROL
REGISTERS
If the user chooses to use the mailbox interrupt function,
four mailbox locations are assigned to each port. These
mailbox locations are external to the memory array. The
mailboxes are accessed by taking
MBSEL
Low while holding
CE
High.
The mailboxes are 16 bits wide: the message is user-
defined since these are addressable SRAM locations. An
interrupt is generated to the opposite port upon writing to the
upper byte of any mailbox location. A port can read the
message it has just written in order to verify it: this read will
not alter the status of the interrupt sent to the opposite port.
The interrupted port can clear the interrupt by reading the
upper byte of the applicable mailbox. This read will not alter
the contents of the mailbox. The use of mailboxes to generate
interrupts to the opposite port and the reading of mailboxes to
clear interrupts is detailed in Truth Table II.
If desired, any of the mailbox interrupts can be indepen-
dently masked via software. Masking of the interrupt sources
is done in the Mask Register. The masks are individual and
independent: a port can mask any combination of interrupt
sources with no effect on the other sources. Each port can
modify only its own Mask Register. The use of this register is
detailed in Truth Table II.
Two registers are provided to permit interpretation of
interrupts: these are the Interrupt Cause Register and the
Interrupt Status Register. The Interrupt Cause Register gives
the user a snapshot of what has caused the interrupt to be
generated - a specific semaphore granted to that port or a
specific mailbox written to by the opposite port. The informa-
tion in this register provides post-mask signals: interrupt
sources that have been masked will not be updated. The
Interrupt Status Register gives the user the status of all bits
that could potentially cause an interrupt regardless of whether
they have been masked. The use of the Interrupt Cause
Register and the Interrupt Status Register is detailed in Truth
Table II.
6.29
4
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE II – MAILBOX INTERRUPTS (
CE
= V
IH
)
(8,9)
MB
SEL
L
L
L
L
L
L
R/
W
X
X
(1)
(1)
(1)
(1)
H
H
H
H
L
L
L
(3)
X
X
UB LB
X
X
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(3)
X
X
X
X
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(3)
X
X
A5
L
A4 A3
L
L
A2
L
A1 A0
L
L
D0
D1
D2 D3
D4
D5
D6 D7
D8
D9 D10 D11 D12 D13 D14 D15
DESCRIPTION
RESERVED (7)
RESERVED (7)
RESERVED (7)
RESERVED (7)
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
X
X
X
X
X
X
X
X
(4)
X
X
X
X
X
X
X
X
(4)
X
X
X
X
X
X
X
X
(4)
X
X
X
X
X
X
X
X
(4)
X
X
X
X
X
X
X
X
(5)
X
X
X
X
X
X
X
X
(5)
X
X
X
X
X
X
X
X
(5)
X
X
X
X
X
X
X
X
(5)
X
X
X
X
X
X
X
X
(6)
X
X
X
X
X
X
X
X
(6)
X
X
X
X
X
X
X
X
(6)
X
X
X
X
X
X
X
X
(6)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX INTERRUPT CONTROLS
RESERVED (7)
RESERVED (7)
RESERVED (7)
H
H
H
H
H
H
RESERVED (7)
3592 tbl 03
NOTES:
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in
either 8-bit or 16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be
individually masked if desired, and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port
can read its own mailboxes to verify the data written, without affecting the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a
particular mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/
W
are stable, the
actual clearing of the interrupt is triggered by the transition of
MBSEL
from V
IH
to V
IL
.
3. This register contains the Mask Register (bits D
0
-D
3
), the Interrupt Cause Register (bits D
4
-D
7
), and the Interrupt Status Register (bits D
8
-D
11
). The
controls for R/
W
,
UB
, and
LB
are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D
12
-D
15
are
"Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing V
IH
to the appropriate bit (D
0
=
Mailbox 0, D
1
= Mailbox 1, D
2
= Mailbox 2, and D
3
= Mailbox 3) disables the interrupt, while writing V
IL
enables the interrupt. All four bits in this
register must be written at the same time. This register can be read at any time to verify the mask settings. The masks are individual and
independent: any single interrupt source can be masked with no effect on the other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading V
OL
for a specific
bit (D
4
= Mailbox 0, D
5
= Mailbox 1, D
6
= Mailbox 2, and D
7
= Mailbox 3) indicates that the associated interrupt source has generated an interrupt.
Acknowledging the interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt
source has been masked, the associated bit in this register will not update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of
whether they have been masked. Reading V
OL
for a specific bit (D
8
= Mailbox 0, D
9
= Mailbox 1, D
10
= Mailbox 2, and D
11
= Mailbox 3) indicates
that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for
this table). This register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this
register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D
0
-D
15
will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these
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