®
ESDA18-1F2
TRANSIL™: Transient Voltage Suppressor
ASD
(Application Specific Devices)
FEATURES AND BENEFITS:
■
■
■
■
■
Stand-off voltage 16V
Unidirectional device
Low clamping factor V
CL
/V
BR
Fast response time
Very thin package: 0.65 mm
Flip-Chip
(4 Bumps)
Table 1: Order Code
Part Number
ESDA18-1F2
Marking
EE
DESCRIPTION
The ESDA18-1F2 is a single line Transil diode
designed specifically for the protection of
integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD &
EOS transient overvoltages.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4
15kV (air discharge)
8kV (contact discharge)
Figure 1: Pin Configuration (ball side)
A
K
B
1
A
2
K
A
K
A
TM:
TRANSIL is a trademark of STMicroelectronics.
May 2005
REV. 1
1/7
ESDA18-1F2
Table 2: Absolute Ratings
(limiting value, per diode)
Symbol
Parameter and test conditions
Peak pulse power dissipation
10 / 1000 µs pulse
Peak pulse power dissipation
8 / 20 µs pulse
Non repetitive surge peak forward current
Maximum operating junction temperature
Storage temperature range
Value
100
T
j
initial = T
amb
700
t
p
=10 ms
T
j
initial = T
amb
8
125
- 65 to + 175
A
°C
°C
W
Unit
P
PP
I
FSM
T
j
T
stg
Table 3: Electrical Characteristics
(T
amb
= 25°C)
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
C
Parameter
Breakdown voltage
Leakage current
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Capacitance
Slope: 1/R
d
I
PP
V
F
V
CL
V
BR
V
RM
I
RM
V
I
F
I
V
BR
Part Number
min.
V
ESDA18-1F2
16
(1)
8 / 20 µs pulse waveform.
I
R
I
RM
max.
V
RM
V
CL
max.
I
PP (1)
V
F (2)
max.
I
F
= 850mA
αT
max.
10
-4
/°C
8.5
C
typ.
V
R
=0V
pF
230
max.
V
18
mA
1
µA
0.5
V
10
V
20
A
1
V
1.3
(2)
DC current not recommended for more than 5 sec. Even if Transil failure mode is short circuit the bumps could exceed melting temper-
ature and the component disassembled from the board.
2/7
ESDA18-1F2
Figure 2: Relative variation of peak pulse
power versus initial junction temperature
P
PP
[T
j
initial] / P
PP
[T
j
initial=25°C)
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
150
100
1000
10000
T
j
initial=25°C
Figure 3: Peak pulse power versus exponen-
tial pulse duration
P
PP
(W)
T
j
(°C)
10
1
10
t
p
(µs)
100
1000
Figure 4: Clamping voltage versus peak pulse
current (typical values, exponential waveform)
I
PP
(A)
100.0
8/20µs
T
j
initial=25°C
Figure 5: Forward voltage drop versus peak
forward current (typical values)
I
FM
(A)
1.E+01
1.E+00
10.0
T
j
=125°C
T
j
=25°C
1.E-01
1.0
1.E-02
V
CL
(V)
0.1
10
12
14
16
18
20
22
24
26
28
30
1.E-03
0.0
0.2
0.4
0.6
0.8
V
FM
(V)
1.0
1.2
1.4
1.6
1.8
2.0
Figure 6: Junction capacitance versus reverse
voltage applied (typical values)
C(pF)
300
F=1MHz
V
OSC
=30mV
RMS
T
j
=25°C
Figure 7: Relative variation of leakage current
versus junction temperature (typical values)
I
R
[T
j
] / I
R
[T
j
=25°C]
100
V
R
=10V
250
200
150
10
100
50
V
R
(V)
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
25
50
T
j
(°C)
75
100
125
3/7
ESDA18-1F2
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery operation. Indeed,
during this operation the device must clamp the DC reverse voltage below 1.3V @ 0.85A (max current).
Thus reverse battery operation has been simulated by inverting the polatrity of the TRANSIL (please see
figures 8 and 9)
Figure 8: Reverse battery operation setup
Equivalent
mobile phone
impedance
PTC
V
mains
I
V
4.7kΩ
1nF
ESDA18-1F2
Figure 9: Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in such real phone
application the ESDA18-1F2 clamp the DC voltage below 1.3V.
Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9V @0.76A DC current:
2
×
V
max
2
×
1.4
-
V
DC
= ----------------------
≈
-----------------
≈
0.9V
Π
3.14
2
×
I
max
2
×
1.2
-
I
DC
= --------------------
≈
-----------------
≈
0.76A
Π
3.14
4/7
ESDA18-1F2
Figure 10: Ordering Information Scheme
ESDA
ESD Array
Breakdown Voltage
18 = 18 Volts max.
Number of line
1 = signle line
Package
F = Flip-Chip
x = 2: Leadfree Pitch = 500µm, Bump = 315µm
Figure 11: FLIP-CHIP Package Mechanical Data
18 - 1
Fx
500µm ± 50
650µm ± 65
315µm ± 50
0.95mm ± 50µm
Figure 12: Foot Print Recommendations
0.95mm ± 50µm
500µm ± 50
Figure 13: Marking
Copper pad Diameter :
250µm recommended , 300µm max
Dot, ST logo
xx = marking
z = packaging location
yww = datecode
(y = year
ww = week)
365
240
365
E
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
All dimensions in µm
x x z
y ww
40
220
5/7
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