HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7024S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
•
•
•
•
•
•
•
•
•
•
more than one device
M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Devices are capable of withstanding greater than 2001V
electrostatic discharge.
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R(1,2)
Address
Decoder
12
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R(2)
2740 drw 01
M/
S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2740/6
6.15
1
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7024 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT7024 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by chip
enable (
CE
) permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technol
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.
The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-
pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited
to military temperature applications demanding the highest
level of performance and reliability.
PIN CONFIGURATIONS
(1,2)
I/O
6L
I/O
5L
I/O
3L
I/O
7L
I/O
4L
I/O
2L
I/O
1L
I/O
0L
GND
SEM
L
R/
L
A
11L
V
CC
CE
L
UB
L
LB
L
OE
L
N/C
A
10L
W
A
9L
INDEX
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3 2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
IDT7024
J84-1
F84-2
84-PIN PLCC /
FLATPACK
TOP VIEW
(3)
68
67
66
65
64
63
62
61
60
59
58
57
56
55
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
BUSY
R
INT
R
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
V
CC
R/
L
SEM
L
I/O
11R
I/O
10R
I/O
15R
CE
R
I/O
12R
I/O
14R
GND
I/O
13R
R/
R
I/O
9R
N/C
A
11R
A
10R
UB
R
LB
R
OE
R
SEM
R
GND
A
9R
A
8R
A
7R
W
2740 drw 02
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
69
7
68
8
67
9
66
10
IDT7024
65
11
PN100-1
64
12
63
13
100-PIN
62
14
TQFP
61
15
TOP VIEW
(3)
60
16
59
17
58
18
57
56
55
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
19
20
21
N/C
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
OE
L
W
UB
L
LB
L
CE
L
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
Index
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
R/
R
GND
UB
R
LB
R
6.15
SEM
R
N/C
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
CE
R
2740 drw 03
W
2
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
(1,2)
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
N/C
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/
W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
INT
L
07
I/O
15L
75
I/O
14L
70
V
CC
74
IDT7024
G84-3
84-PIN PGA
TOP VIEW
(3)
BUSY
L
32
A
0L
31
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/
S
29
INT
R
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
0R
BUSY
R
27
26
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/
15
W
R
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
N/C
H
A
10R
J
A
9R
K
A
7R
L
2740 drw 04
Index
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2740 tbl 1
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
CE
L
R/
W
L
OE
L
A
0L
– A
11L
I/O
0L
– I/O
15L
CE
R
R/
W
R
OE
R
A
0R
– A
11R
I/O
0R
– I/O
15R
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2740 tbl 02
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
UB
R
LB
R
INT
R
BUSY
R
GND
6.15
3
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
X
L
L
L
L
L
L
X
R/
W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
Both Bytes Deselected
Mode
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
DATA
OUT
Read Lower Byte Only
High-Z
Outputs Disabled
2740 tbl 03
DATA
OUT
DATA
OUT
Read Both Bytes
NOTE:
1. A
0L
— A
11L
are not equal to A
0R
— A
11R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
H
X
H
X
L
L
R/
W
H
H
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
I/O
0-7
Mode
DATA
OUT
DATA
OUT
Read Semaphore Flag Data Out
DATA
OUT
DATA
OUT
Read Semaphore Flag Data Out
DATA
IN
DATA
IN
—
—
DATA
IN
DATA
IN
—
—
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
u
u
X
X
2740 tbl 04
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
- I/O
15
). These eight semaphores are addressed by A
0
- A
2
.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
(2)
0.8
V
V
V
V
2740 tbl 06
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
V
IL
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
NOTES:
2740 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc +0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20ma for the period over V
TERM >
Vcc
+ 0.5V
.
(T
A
= +25°C, F = 1.0MHZ) TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Condition
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
CAPACITANCE
(1)
NOTES:
2740 tbl 07
1. This parameter are determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.15
4
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
IDT7024S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
IDT7024L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2740 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 5.0V
±
10%)
Symbol
Parameter
Dynamic Operating
I
CC
Current
(Both Ports Active)
Test
Condition
CE
"A"
=V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
7024X15
7024X17
7024X20
Com'l. Only
Com'l. Only
(2)
Version Typ. Max. Typ.
(2)
Max. Typ.
(2)
Max.
MIL S
—
—
—
—
160
370
L
—
—
—
—
160
320
COM S
L
MIL
S
L
170
170
—
—
20
20
—
—
105
105
—
—
1.0
0.2
—
—
100
100
310
260
—
—
60
50
—
—
190
160
—
—
15
5
—
—
170
140
170
170
—
—
20
20
—
—
105
105
—
—
1.0
0.2
—
—
100
100
310
260
—
—
60
50
—
—
190
160
—
—
15
5
—
—
170
140
160
160
20
20
20
20
95
95
95
95
1.0
0.2
1.0
0.2
90
90
90
90
290
240
90
70
60
50
240
210
180
150
30
10
15
5
225
200
155
130
7024X25
Typ.
(2)
Max. Unit
155
340
mA
155
280
155
155
16
16
16
16
90
90
90
90
1.0
0.2
1.0
0.2
85
85
85
85
265
220
80
65
60
50
215
180
170
140
30
10
15
5
200
170
145
120
mA
mA
mA
mA
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX(3)
COM S
L
MIL
S
L
COM S
L
MIL
S
L
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
CE
"A"
=V
IL
and
CE
"B"
=V
IL(5)
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
I
SB3
Full Standby Current Both Ports
CE
L
and
(Both Ports — All
CE
R
>V
CC
- 0.2V
COM S
CMOS Level Inputs) V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
L
SEM
R
=
SEM
L
> V
CC
- 0.2V
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
CE
"A"
< 0.2 and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Open,
f = f
MAX(3)
MIL
S
L
COM S
L
NOTES:
2740 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CC DC
= 120mA (typ.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/ t
RC
, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.15
5
FPGA/CPLD
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