TJA1027
ISO 17987/LIN 2.x/SAE J2602 transceiver
Rev. 3 — 18 December 2018
Product data sheet
1. General description
The TJA1027 is the interface between the Local Interconnect Network (LIN) master/slave
protocol controller and the physical bus in a LIN network. It is primarily intended for
in-vehicle sub-networks using baud rates up to 20 kBd and is compliant with LIN 2.0,
LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V). The TJA1027 is
pin-compatible with the TJA1020, TJA1021, TJA1022, TJA1029 and MC33662(B).
The transmit data stream generated by the protocol controller is converted by the
TJA1027 into an optimized bus signal shaped to minimize ElectroMagnetic Emissions
(EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a
master application, an external resistor in series with a diode should be connected
between pin V
BAT
and pin LIN. The receiver detects a receive data stream on the LIN bus
input pin and transfers it via pin RXD to the microcontroller.
Power consumption is very low in Sleep mode. However, the TJA1027 can still be woken
up via pins LIN and SLP_N.
2. Features and benefits
2.1 General
LIN 2.x/ISO 17987-4:2016 (12 V)/SAE J2602 compliant
Baud rate up to 20 kBd
Very low ElectroMagnetic Emissions (EME)
Very low current consumption in Sleep mode with remote LIN wake-up
Input levels compatible with 3.3 V and 5 V devices
Integrated termination resistor for LIN slave applications
Passive behavior in unpowered state
Operational during cranking pulse: full operation from 5 V upwards
Undervoltage detection
K-line compatible
Available in SO8 and HVSON8 packages
Leadless HVSON8 package (3.0 mm × 3.0 mm) with low thermal resistance
supporting Automated Optical Inspection (AOI) capability
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
Pin-compatible subset of the TJA1020, TJA1021, TJA1022 and MC33662(B)
Pin- and footprint-compatible with the TJA1029
NXP Semiconductors
TJA1027
ISO 17987/LIN 2.x/SAE J2602 transceiver
2.2 Protection
Very high ElectoMagnetic Immunity (EMI)
Very high ESD robustness:
8
kV according to IEC 61000-4-2 for pins LIN and V
BAT
Bus terminal and battery pin protected against transients in the automotive
environment (ISO 7637)
Bus terminal short-circuit proof to battery and ground
Thermally protected
Initial transmit data (TXD) dominant check
3. Quick reference data
Table 1.
V
BAT
I
BAT
Quick reference data
Conditions
limiting values
operating range
battery supply current
Sleep mode; V
LIN
= V
BAT
; V
SLP_N
= 0 V
Standby mode; V
LIN
= V
BAT
; V
SLP_N
= 0 V
Normal mode; V
LIN
= V
BAT
; V
SLP_N
= 5 V;
V
TXD
= 5 V
V
LIN
V
ESD
T
vj
voltage on pin LIN
electrostatic discharge voltage
virtual junction temperature
limiting value with respect to GND and
V
BAT
on pin LIN; according to IEC 61000-4-2
limiting value
Min
0.3
5
2.5
2.5
200
42
8
40
Typ
-
-
7
7
800
-
-
-
Max
+42
18
10
10
1600
+42
+8
+150
Unit
V
V
A
A
A
V
kV
C
battery supply voltage
Symbol Parameter
4. Ordering information
Table 2.
Ordering information
Package
Name
TJA1027T/20
TJA1027TK/20
SO8
HVSON8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3
3
0.85 mm
Version
SOT96-1
SOT782-1
Type number
TJA1027
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2018
2 of 24
NXP Semiconductors
TJA1027
ISO 17987/LIN 2.x/SAE J2602 transceiver
5. Block diagram
TJA1027
POWER-ON RESET &
UNDERVOLTAGE DETECTION
RXD
1
BUS
TIMER
6
SLP_N
2
CONTROL
LIN
7
V
BAT
TXD
4
5
TEMPERATURE
PROTECTION
015aaa212
GND
Fig 1.
Block diagram
TJA1027
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2018
3 of 24
NXP Semiconductors
TJA1027
ISO 17987/LIN 2.x/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
TJA1027T
RXD
SLP_N
n.c.
TXD
1
2
3
4
015aaa213
terminal 1
index area
8
7
6
5
n.c.
V
BAT
LIN
GND
RXD
SLP_N
n.c.
TXD
1
2
3
4
TJA1027TK
8
7
6
5
015aaa214
n.c.
V
BAT
LIN
GND
Transparent top view
a. TJA1027T/20: SO8 package
Fig 2.
Pin configuration diagrams
b. TJA1027TK/20: HVSON8 package
6.2 Pin description
Table 3.
Symbol
RXD
SLP_N
n.c.
TXD
GND
LIN
V
BAT
n.c.
[1]
Pin description
Pin
1
2
3
4
5
[1]
6
7
8
Description
receive data output (open-drain); active LOW after a wake-up event
sleep control input (active LOW); resets wake-up request on RXD
not connected
transmit data input
ground
LIN bus line input/output
battery supply
not connected
For enhanced thermal and electrical performance, solder the exposed center pad of the HVSON8 package
to board ground.
TJA1027
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2018
4 of 24
NXP Semiconductors
TJA1027
ISO 17987/LIN 2.x/SAE J2602 transceiver
7. Functional description
The TJA1027 is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN network. According to the Open System Interconnect (OSI) model,
this is the LIN physical layer.
The LIN transceiver is optimized for, but not limited to, automotive applications with
excellent ElectroMagnetic Compatibility (EMC) performance.
7.1 LIN 2.x/ISO 17987-4:2016 (12 V)/SAE J2602 compliant
The TJA1027 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and
ISO 17987-4:2016 (12 V) compliant. The LIN physical layer is independent of higher OSI
model layers (e.g. the LIN protocol). Consequently, nodes containing an
ISO 17987-4:2016 (12 V) compliant physical layer can be combined, without restriction,
with LIN physical layer nodes that comply with earlier revisions (LIN 1.0, LIN 1.1, LIN 1.2,
LIN 1.3, LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A).
7.2 Operating modes
The TJA1027 supports modes for normal operation (Normal mode) and very-low-power
operation (Sleep mode). An intermediate wake-up mode between Sleep and Normal
modes is also supported (Standby mode). The state diagram is shown in
Figure 3.
TJA1027
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2018
5 of 24
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