HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
Integrated Device Technology, Inc.
IDT70121S/L
IDT70125S/L
FEATURES:
• High-speed access
– Commercial: 25/35/45/55ns (max.)
• Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
•
BUSY
output flag on Master;
BUSY
input on Slave
•
INT
flag for port-to-port communication
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by
CE
, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
OE
R
R/
W
R
CE
R
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
11
(1,2)
A
10L
A
0L
MEMORY
ARRAY
Address
Decoder
A
11R
A
0R
11
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-
stated push-pull
output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is totem-pole
output.
CE
L
OE
L
R/
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
INT
L(2)
INT
R
2654 drw 01
(2)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2654/4
6.10
1
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Cont'd):
Fabricated using IDT’s CMOS high-performance
technology, these devices typically operate on only 500mW of
power. Low-power (L) versions offer battery backup data
retention capability with each port typically consuming 200µW
from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin
PLCC.
PIN CONFIGURATIONS
(1,2)
W
L
W
R
R/
INT
R
INT
L
R/
V
CC
A
10R
A
10L
CE
L
CE
R
A
0L
OE
L
INDEX
BUSY
R
BUSY
L
21
22
23
24
25
26
27
28
29
30
31
32
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
33
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
9
10
11
12
13
14
15
16
17
18
19
20
1
8
46
45
44
43
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
8R
I/O
7R
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
Grade
Commercial
Ambient Temperature
0°C to +70°C
GND
0V
V
CC
5.0V
±
10%
2654 tbl 02
51
50
7
6
3
52
49
5
2
48
4
IDT70121/125
J52-1
PLCC
TOP VIEW
(3)
47
42
41
40
39
38
37
36
35
34
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5
0
–
–
Max.
5.5
0.0
6.0
(2)
0.8
Unit
V
V
V
V
2654 tbl 03
2654 drw 02
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the orientation of the actual part-marking.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
(2)
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)
Unit
V
°C
°C
°C
mA
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Condition
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
Rating
Terminal Voltage
with Respect to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
50
NOTES:
2654 tbl 13
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
NOTES:
2654 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+
0.5V.
6.10
2
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
70121S
70125S
Min. Max.
—
—
—
2.4
10
10
0.4
—
70121L
70125L
Min. Max. Unit
—
—
—
2.4
5
5
0.4
—
µA
µA
V
V
2654 tbl 04
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(5)
(5)
Test Condition
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
CC
= 5.5V,
CE
= V
IH
V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= –4mA
Output Leakage Current
Output Low Voltage
Output High Voltage
NOTE:
1. At Vcc < 2.0V leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1,4)
(V
CC
= 5V
±
10%)
Symbol
I
CC
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current
(Both Ports—TTL
Level Inputs)
Standby Current
(One Port—TTL
Level Inputs)
Full Standby
Current (Both Ports
CMOS Level Inputs)
Full Standby
Current (One Port
CMOS Level Inputs)
Test
Condition
70121X25
70125X25
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Version
Com’l.
S
L
S
L
S
L
S
L
S
L
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
125 260 125 250 125 245 125 240
125 220 125 210 125 205 125 200
30
30
80
80
1.0
0.2
70
70
65
45
175
145
15
5
170
140
30
30
80
80
1.0
0.2
70
70
65
45
165
135
15
5
160
130
30
30
80
80
1.0
0.2
70
70
65
45
160
130
15
5
155
125
30
30
80
80
1.0
0.2
70
70
65
45
155
125
15
5
150
120
mA
CE
= V
IL
,Outputs Open,
f = f
MAX(2)
I
SB1
CE
"A"
and
CE
"B"
= V
IH
,
f = f
MAX
(2)
Com’l.
mA
I
SB2
CE
"A"
=V
IL
and
CE
"B"
=V
IH(5)
Active Port Outputs Open,
f = f
MAX(2)
V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V, f = 0
(3)
Com’l.
mA
I
SB3
CE
"A"
and
CE
"B"
≥
V
CC
– 0.2V,
CE
"A"
<0.2V and
CE
"B"
>VCC-0.2V
(5
)
Com’l.
mA
I
SB4
Com’l.
mA
V
IN
≥
V
CC
– 0.2V or
V
IN
≤
0.2V, Active Port
Outputs Open, f = f
MAX(2)
NOTES:
1. “X” in part numbers indicates power rating (S or L).
2. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST
CONDITIONS” of input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, T
A
=+25°C for Typical values, and they are not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
2654 tbl 05
6.10
3
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS
(L Version Only)
70121L/70125L
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Test Condition
V
CC
= 2.0V,
CE
≥
V
CC
– 0.2V
V
IN
≥
V
CC
– 0.2V or V
IN
≤
0.2V
Com’l.
Min.
2
—
0
t
RC(2)
Typ.
(1)
—
100
—
—
Max.
—
1500
—
—
Unit
V
µA
ns
ns
2654 tbl 06
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and are not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
4.5V
t
CDR
V
DR
≥
2V
4.5V
t
R
V
DR
V
IH
2654 drw 03
CE
V
IH
5V
5V
1250Ω
1250Ω
DATA
OUT
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 07
DATA
OUT
BUSY
INT
775Ω
30pF
775Ω
5pF
2654 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(
For t
LZ,
t
HZ,
t
WZ,
t
OW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(3)
70121X25
70125X25
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Symbol
Parameter
Read Cycle
t
RC
Read Cycle Time
t
AA
Address Access Time
t
ACE
Chip Enable Access Time
t
AOE
Output Enable Access Time
t
OH
Output Hold from Address Change
t
LZ
Output Low-Z Time
(1,2)
t
HZ
Output High-Z Time
(1,2)
t
PU
Chip Enable to Power-Up Time
(2)
t
PD
Chip Disable to Power-Down Time
(2)
Min. Max. Min. Max. Min. Max. Min. Max. Unit
25
—
—
—
0
0
—
0
—
—
25
25
12
—
—
10
—
50
35
—
—
—
0
0
—
0
—
—
35
35
25
—
—
15
—
50
45
—
—
—
0
0
—
0
—
—
45
45
30
—
—
20
—
50
55
—
—
—
0
0
—
0
—
—
55
55
35
—
—
30
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition is measured
±500mV
from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. “X” in part numbers indicates power rating (S or L).
2654 tbl 08
6.10
4
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
2654 drw 05
t
OH
BUSY
OUT
t
BDD
(3,4)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(5,6)
t
ACE
CE
t
AOE
(4)
t
HZ
(2)
OE
t
LZ
DATA
OUT
t
LZ
I
CC
CURRENT
I
SS
t
PU
(1)
(1)
t
HZ
VALID DATA
t
PD
(4)
(2)
50%
50%
2654 drw 06
NOTES:
1. Timing depends on which signal is aserted last,
OE
or
CE
.
2. Timing depends on which signal is deaserted first,
OE
or
CE
.
3. t
BDD
delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY
has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, t
AOE
,
t
ACE
,
t
AA
, or
t
BDD
.
5. R/
W
= V
IH,
and the address is valid prior to other coincidental with
CE
transition Low.
6. R/
W
= V
IH,
CE
= V
IL, and
OE
= V
IL.
Address is valid prior to or coincident with
CE
transition Low.
6.10
5
FPGA/CPLD
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