HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7005S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial:15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7005L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7005 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of Semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 68-pin PGA, 68-pin quad flatpack, 68-pin
PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.
The IDT7005 is designed to be used as a stand-alone Dual-
Port RAM or as a combination MASTER/SLAVE Dual-Port
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
R/
CE
L
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
13
(1,2)
A
12L
A
0L
MEMORY
ARRAY
Address
Decoder
A
12R
A
0R
13
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
(2)
SEM
L
(2)
INT
L
M/
S
INT
R
2738 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2738/6
6.06
1
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RAM for 16-bit-or-more word systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, a 68-
pin quad flatpack, a 68-pin PLCC and a 64-pin Thin Plastic
Quad Flatpack (TQFP). Military grade product is manufac-
tured in compliance with the latest revision of MIL-STD-883,
Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
PIN CONFIGURATIONS
(1,2)
I/O
1L
I/O
0L
N/C
SEM
L
4
W
L
R/
6
5
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
8
7
3
N/C
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
OE
L
CE
L
IDT7005
J68-1
F68-1
PLCC / FLATPACK
TOP VIEW
(3)
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
BUSY
R
INT
R
GND
M/
S
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
0R
A
1R
A
2R
A
3R
A
4R
I/O
7R
N/C
SEM
R
N/C
N/C
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
W
R
CE
R
R/
L
SEM
L
I/O
1L
I/O
0L
INDEX
59
58
57
64
63
62
56
55
54
53
52
61
60
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
1
2
3
4
5
6
7
8
9
51
50
49
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
OE
L
2738 drw 02
CE
L
R/
W
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
IDT7005
PN-64
TQFP
TOP VIEW
(3)
BUSY
L
GND
M/
S
10
11
12
13
14
15
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
20
21
22
23
24
25
17
18
19
26
27
28
29
30
31
A
7R
A
8R
A
6R
I/O
6R
I/O
7R
SEM
R
A
12R
R/
R
A
11R
A
10R
CE
R
OE
R
GND
A
9R
A
5R
N/C
32
16
33
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the the actual part-marking.
6.06
W
2738 drw 03
2
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CON'T.)
(1,2)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/
S
45
40
38
A
1R
INT
R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
61
60
N/C
N/C
63
07
IDT7005
G68-1
68-PIN PGA
TOP VIEW(3)
28
29
A
11R
A
10R
26
27
GND A
12R
24
N/C
25
N/C
23
06
05
SEM
L
CE
L
OE
L
R/
W
L
64
62
65
04
SEM
R
20
22
CE
R
03
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
5L
I/O
3L
B
C
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
OE
R
21
R/
R
W
02
18
19
I/O
7R
N/C
17
I/O
6R
K
L
2738 drw 04
01
A
INDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate oriention of the actual part-marking
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2738 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
12L
I/O
0L
– I/O
7L
CE
R
R/
W
R
OE
R
A
0R
– A
12R
I/O
0R
– I/O
7R
SEM
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
INT
R
BUSY
R
GND
6.06
3
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
CE
Outputs
SEM
R/
W
X
L
H
X
OE
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
H
L
L
X
NOTE:
X
X
L
H
H
H
H
X
2738 tbl 02
1. A
0L
— A
12L
is not equal to A
0R
— A
12R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
CE
Outputs
SEM
R/
W
OE
I/O
0-7
DATA
OUT
DATA
IN
—
Write I/O
0
into Semaphore Flag
Not Allowed
Mode
Read in Semaphore Flag Data 0ut
H
H
L
u
X
H
L
X
X
L
L
L
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0 -
I/O
15
. These eight semaphores are addressed by A
0
- A
2.
2738 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2738 tbl 05
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
Commercial
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
(2)
0.8
V
V
V
V
2738 tbl 06
NOTES:
2738 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10% maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz) TQFP PACKAGE
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
Max.
V
IN
= 3dV
V
OUT
= 3dV
9
10
Unit
pF
pF
NOTES:
2738 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.06
4
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
IDT7005S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
IDT7005L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2738 tbl 08
Min.
—
—
—
2.4
Max.
10
10
0.4
—
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 5.0V
±
10%)
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
I
SB3
CE
SEM
Test
Condition
= V
IL
, Outputs Open
= V
IH
Version
MIL.
S
L
7005X15
Com'l. Only
Typ.
(2)
Max.
—
—
170
160
—
—
20
10
—
—
105
95
—
—
1.0
0.2
—
—
100
90
—
—
310
260
—
—
60
60
—
—
190
160
—
—
15
5
—
—
170
140
7005X17
Com'l. Only
Typ.
(2)
Max.
—
—
170
160
—
—
20
10
—
—
105
95
—
—
1.0
0.2
—
—
100
90
—
—
310
260
—
—
60
50
—
—
190
160
—
—
15
5
—
—
170
140
7005X20
Typ.
(2)
Max.
160
150
160
150
20
10
20
10
95
85
95
85
1.0
0.2
1.0
0.2
90
80
90
80
370
320
290
240
90
70
60
50
240
210
180
150
30
10
15
5
225
200
155
130
7005X25
Typ.
(2)
Max. Unit
155
145
155
145
16
10
16
10
90
80
90
80
1.0
0.2
1.0
0.2
85
75
85
75
340
280
265
220
80
65
60
50
215
180
170
140
30
10
15
5
200
170
145
120
mA
mA
mA
mA
mA
f = f
MAX(3)
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
CE
L
COM. S
L
MIL.
S
L
f = f
MAX(3)
CE
"A"=
COM. S
L
MIL.
S
L
COM. S
L
MIL.
S
L
V
IL
and
CE
"B"=
V
IH(5)
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
> V
IH
Full Standby Current Both Ports
CE
L
and
(5)
(Both Ports — All
CE
R
> V
CC
- 0.2V
CMOS Level Inputs) V
IN
> V
CC
- 0.2V or
COM. S
V
IN
< 0.2V, f = 0
(4)
L
SEM
R
=
SEM
L
> V
CC
- 0.2V
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
< 0.2V and
MIL.
> V
CC
- 0.2v
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
COM.
V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX(3)
CE"
B"
CE"
B"
S
L
S
L
NOTES:
2738 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CC DC
= 120mA typ.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
6.06
5
模拟与混合信号
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