2.5 Gbit/s
16:1 Multiplexer
GD16507
Preliminary
General Information
The GD16507 is a high performance
2.5 Gbit/s 16:1 Multiplexer with on-chip
VCO and PLL – sytem. Designed for use
in ITU-T STM16 or SONET OC-48 fiber
optic communication systems.
The GD16507 multiplexes sixteen
155 Mbit/s data streams into a single
2.5 Gbit/s data stream output using an
external reference clock at 155.52 MHz
or 77.6 MHz.
The output bit rate of the GD16507
covers the frequency range 2.3-2.7 GHz
depending on the reference clock fre-
quency.
A selecable high-speed data input allows
direct 2.5 Gbit/s input to the 2.5 Gbit out-
put (no retiming).
Internal clock synchronisation is provided
by an on-chip PLL circuit requiring a sim-
ple passive external loop filter. The PLL
circuit features an NLDET pin output for
simple implementation of a lock detect
function, as shown overleaf.
The GD16507 is manufactured in a
Silicon Process .
The GD16507 requires a single -5.2 V
supply.
Features
l
SDH STM-16, SONET OC-48
compatible.
l
On-chip PLL containing low jitter
2.5 GHz VCO, phase/frequency
detector and charge pump.
l
PLL lock detect output.
l
Single -5.2 V supply operation.
l
Differential ECL 2.5 GHz clock and
2.5 Gbit data output.
clock inputs.
l
Differential ECL compatible data and
l
Power dissipation: 1.0 W (typ.).
SEL4
SIP
SIN
l
Packaged in:
–
–
144 ld fpBGA
68 pin MLC
DIP0
DIN0
MUX
DIP15
DIN15
LOAD
SOP
SON
Applications
l
Tele Communications systems:
–
–
SDH STM-16
SONET OC-48
FCK
FCKN
CKOUT
CKOUN
REFCK
REFCN
SEL2
SEL3
VCO
V
U
U
l
Data Communications
PFC
R
D
CHAP
D
VDD
VEE
VDDA
VEEA
Clock
Gen.
VCTL TCK SELTCK
NLDET
PFCO
Data Sheet Rev. 03
Application Details
PLL Loop Filter and
PLL Reset
Based on GIGA’s experience with the
PLL in the GD16507, GIGA recommends
use of a loop filter, as shown in the figure
below. This loop filter is used in the AC
production test set-up and has been
found to ensure that the jitter perfor-
mance of GD16507 is within ITU specifi-
cations. Loop filter component values
TBD.
Resistor (R1) connected between the
pins PFCO and VCTL, helps to linearise
the current source in the charge pump.
Resistor (R2) and capacitor (C1) com-
prise the loop filter. These components
have been shown to give optimum PLL
performance under test, with jitter well
within the specifications. The optimum
choice of component values with regard
to jitter is affected by the reference clock
phase-noise performance.
Lock Detect Circuit
A simple PLL lock detect function can be
implemented by 3 external components
(R3, C3 and ST1), comprising a low-pass
filter followed by a Schmitt trigger, as
shown in the figure below.
NLDET / 6
R3
C3
ST1
LOCK
PFC
PFCO / 3
VCO
R1
VCTL / 2
R2
C1
VDD/VDDA
Figure 1.
PLL Loop Filter
For noise and jitter reasons it is very im-
portant that C1 is connected to VDD/
VDDA in close proximity of the VCTL pin.
Data Sheet Rev. 03
GD16507
Page 2
Pin List
Mnemonic:
DIP0,
DIP1,
DIP2,
DIP3,
DIP4,
DIP5,
DIP6,
DIP7,
DIP8,
DIP9,
DIP10,
DIP11,
DIP12,
DIP13,
DIP14,
DIP15,
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
Pin Number
144EA
68BA
A7, B7
A8, B8
A9, B9
A10, B10
A12, B12
C12, D11
D12, E11
E12, F11
H12, J12
L12, K12
M11, M12
M10, L10
M9, L9
M8, L9
M7, L7
M6, L6
C1, D1
A1, A2
G1
8, 7
11, 10
13, 12
16, 15
20, 19
23, 22
25, 24
28, 27
33, 32
37, 36
40, 39
42, 41
45, 44
47, 46
50, 49
54, 53
63, 62
67, 66
N/A
Pin Type:
ECL IN
Description:
Differential data inputs. Shifted to the serial output starting with
DI15, followed by DI14, DI13....
SIP, SIN
REFCK, REFCN
SEL1
CML IN
ECL IN
ECL IN
Differential serial input. High speed self-terminating input to be
used in conjunction with GD16504 for remote/line loop bac
k.
Reference clock differential input for PLL.
Select signal for reference clock frequency. When high,
155.52 MHz is selected; when low, 77.76 MHz. Bonded high for
155.52 MHz option in 68BA version.
Phase relation select between positive going edge of CKOUT and
sample time of input data:
SEL3,
1
1
0
0
SEL2
1
0
1
0
T
T
T
T
DEL
DEL
DEL
DEL
SEL2
SEL3
B2
H11
6
N/A
ECL IN
= 0E
= 90E
= 180E
= 270E
SEL3 is bounded high in 68BA version.
SEL4
VCTL
TCK
SOP, SON
FCK, FCKN
CKOUT, CKOUN
PFCO
J1, K1
F1, G1
F12, G12
A5
M4
A4
35
2
64
57, 56
58, 59
29, 30
3
ECL IN
Anl. IN
ECL IN
ECL OUT
ECL OUT
ECL OUT
Anl. OUT
Select between MUX or Serial Input as source for the output
buffer. When high, MUX is selected; low, Serial Input.
VCO voltage control input.
Test clock input. Replaces the VCO as clock source when
SELTCK is set to high.
Differential Serial Output, 2.488 Gbit/s.
Differential Serial Clock Output, 2.5 GHz.
155.52 MHz subdivided VCO-clock. Phase relation between this
output and sample point of input data configurable by SEL2, 3.
Phase/ frequency comparator output. Changes between Drive
High - Tristate - Drive Low according to VCO phase and freq. with
respect to REFCK.
Inverted Lock Detect output. Refer to Figure 1on
page 2
for
connection.
Select TCK for Clock input. For DC test only.
Connect to VEE for normal operation.
0 V Power for core and ECL I/O.
NLDET
SELTCK
VDD
B6
J11
6
17
Anl. OUT
ECL IN
PWR
B1, C2, D2, 4, 9, 14, 21,
D4..D9, E1, 26, 31, 38,
43, 48, 55,
E2, E4..9,
60, 65
F2, F4..9,
G2, G4..9,
H1, H2,
H4..H9, J2,
J4..9, K2, L1
Data Sheet Rev. 03
GD16507
Page 3
Mnemonic:
VEE
Pin Number
144EA
68BA
C3..9, D3,
D10, E3,
E10, F3,
F10, G3,
G10, H3,
H10, J3,
J10, K3..9,
M3
B4, B5
A3, A6
A11, B11,
C11, K10,
K11, L2..5,
L11, M1, M2
34, 52
Pin Type:
PWR
Description:
-5 V Power for core and ECL I/O.
VDDA
VEEA
NC
1
18, 68
5, 51
PWR
PWR
NC
0 V Power for VCO.
-5 V Power for VCO.
Not connected.
Data Sheet Rev. 03
GD16507
Page 4
Package Pinout
1
A
B
C
D
E
F
G
H
J
K
L
M
NC
P
SO
SO
N
N
CK
F
K
FC
SIP
SIN
R
C
EF
K
R
2
N
FC
E
3
E
VE
A
4
T
VC
V
L
5
C
PF
V
O
6
E
VE
N
A
T
7
IP0
D
0
IN
D
VE
E
8
IP1
D
N
DI
VE
1
9
IP2
D
N
DI
VE
2
10
IP3
D
N
DI
VE
3
11
NC
NC
NC
N
DI
5
6
7
1
12
IP4
D
4
IN
D
IP5
D
DI
P6
A
B
C
D
E
F
G
H
J
K
L
M
2
EL
S
K
TC
E
VE
E
VE
E
VE
E
VE
E
VE
E
VE
E
VE
E
VE
A
DD
A
DD
E
LD
E
E
VE
E
VE
VE
E
E
E
E
E
VE
VE
N
DI
P7
DI
T
OU
CK
N
OU
CK
P8
DI
DI
N8
9
E
VE
E
VE
VE
E
N
DI
L
SE
SE
L3
K
E
VE
VE
E
E
VE
NC
L
SE
4
VE
E
5
VE
E
4
VE
N
DI
E
VE
N
DI
E
NC
N
DI
11
TC
SL
NC
NC
N
DI
NC
NC
NC
E
VE
NC
NC
1
IN
D
IP1
D
1
IN
D
IP1
D
13
12
P9
DI
5
4
0
3
0
2
1
IP1 DIP1 DIP1 DIP1 DIN1
D
1
2
3
4
5
6
7
8
9
10
11
12
(Empty) = VDD
Figure 2.
Package Pinout - 144EA, Top View
Note:
Please note that this pinout is under design and can be changed.
Data Sheet Rev. 03
GD16507
Page 5
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