Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
7C138-15
7C139-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
GND < V
I
< V
CC
Output Disabled, GND < V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA,
Outputs Disabled
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
Both Ports
CE and CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
[7]
One Port
CE
L
or CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V, Active
Port Outputs, f = f
MAX[7]
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
125
15
130
60
–10
–10
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
0.8
+10
+10
220
–10
–10
Min.
2.4
0.4
2.2
0.8
+10
+10
180
190
40
50
110
120
15
30
100
115
mA
mA
mA
mA
Max.
7C138-25
7C139-25
Min.
2.4
0.4
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
I
SB2
I
SB3
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
I
SB4
Standby Current
(One Port CMOS Level)
Notes:
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby I
SB3
.
Document #: 38-06037 Rev. *B
Page 3 of 16
CY7C138
CY7C139
Electrical Characteristics
Over the Operating Range (continued)
]
7C138-35
7C139-35
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
GND < V
I
< V
CC
Output Disabled, GND < V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA,
Outputs Disabled
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
Both Ports
CE and CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
[7]
One Port
CE
L
or CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V, Active
Port Outputs, f = f
MAX[7]
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
–10
–10
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
0.8
+10
+10
160
180
30
40
100
110
15
30
90
100
Min.
2.4
0.4
Max.
7C138-55
7C139-55
Min.
2.4
0.4
2.2
0.8
–10
–10
+10
+10
160
180
30
40
100
110
15
30
90
100
mA
mA
mA
mA
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
I
SB2
I
SB3
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
I
SB4
Standby Current
(One Port CMOS Level)
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
15
Unit
pF
pF
AC Test Loads and Waveforms
5V
R1 = 893Ω
OUTPUT
C = 30 pF
R2 = 347Ω
OUTPUT
C = 30pF
V
TH
= 1.4V
(a) Normal Load (Load 1)
(b) Thévenin EquivalentLoad 1)
(
ALL INPUT PULSES
OUTPUT
C = 30 pF
3.0V
GND
10%
90%
90%
10%
< 3 ns
(c) Three-State Delay (Load 3)
5V
R1 = 893Ω
OUTPUT
C = 5 pF
R2 = 347Ω
R
TH
= 250Ω
< 3 ns
Load (Load 2)
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06037 Rev. *B
Page 4 of 16
CY7C138
CY7C139
Switching Characteristics
Over the Operating Range
[9]
7C138-15
7C139-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
3
10
3
10
0
15
15
12
12
2
0
12
10
0
10
3
30
25
15
15
15
15
5
0
13
Note 15
5
0
20
Note 15
3
50
30
20
20
20
20
5
0
30
Note 15
25
20
20
2
0
20
15
0
15
3
60
35
20
20
20
20
5
0
40
Note 15
0
25
35
30
30
2
0
25
15
0
20
3
70
40
45
40
40
35
3
15
0
35
55
40
40
2
0
30
20
0
25
3
15
10
3
15
3
20
0
55
15
15
3
25
15
3
20
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C138-25
7C139-25
Min.
Max.
7C138-35
7C139-35
Min.
Max.
7C138-55
7C139-55
Min.
Max.
Unit
t
LZOE[10,11,12]
OE Low to Low Z
t
HZOE[10,11,12]
OE HIGH to High Z
t
LZCE[10,11,12]
CE LOW to Low Z
t
HZCE[10,11,12]
t
PU[12]
t
PD[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE[11,12]
t
LZWE[11,12]
t
WDD[13]
t
DDD[13]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[15]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
WRITE CYCLE
BUSY TIMING
[14]
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
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