NATIONAL HYBRID, Inc.
NHi-156XX Terminals
NHi-157XX Terminals
Bus Controller, Remote Terminal, Bus Monitor
PCI Bus And Local Bus Host Interface
User's Manual
Version 2006.06.14
June 2006
The
information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL
HYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications
are subject to change without notice.
2200 Smithtown Avenue, Ronkonkoma, NY 11779
Telephone (631) 981- 2400
Data Bus Fax (631) 981- 2445
Website http: //www.nationalhybrid.com
Email: databus@nationalhybrid.com
-
1
-
1.0.0
2.0.0
3.0.0
3.1.0
3.1.1
3.1.2
3.1.3
3.1.4
3.2.0
SCOPE......................................................................................................................................... 7
NHi-156XX PROTOCOL COMPLIANCE.............................................................................. 7
INTRODUCTION ...................................................................................................................... 7
FEATURES
............................................................................................................................. 7
GENERAL FEATURES ...................................................................................................... 7
Bus Controller Highlights..................................................................................................... 8
Remote Terminal Highlights ................................................................................................ 9
Bus Monitor Highlights ........................................................................................................ 9
BLOCK DIAGRAMS............................................................................................................... 10
3.3.0
PROTOCOL CHIP DESCRIPTION ....................................................................................... 11
3.3.1
HOST BUS INTERFACE UNIT........................................................................................ 11
3.3.2
MEMORY MANAGEMENT INTERFACE UNIT ........................................................... 12
3.3.3
INTERRUPT CONTROL UNIT ........................................................................................ 12
3.3.3.1
ICU REGISTERS .......................................................................................................... 12
3.3.3.2
ICU FIFO....................................................................................................................... 13
3.3.4
DUAL REDUNDANT FRONT END ................................................................................ 13
3.3.4.1
MANCHESTER DECODER ........................................................................................ 13
3.3.4.2
MANCHESTER ENCODER ........................................................................................ 13
3.3.4.3
GAP COUNTER ........................................................................................................... 14
3.3.4.4
RT - RT NO RESPONSE COUNTER .......................................................................... 14
3.3.4.5
MINIMUM RESPONSE TIME COUNTER................................................................. 14
3.3.4.6
FAIL -SAFE TIMEOUT COUNTER............................................................................ 14
3.3.5
MESSAGE PROCESSOR UNIT ....................................................................................... 14
3.3.6
PCI INTERFACE UNIT..................................................................................................... 14
3.4.0
RT HARDWIRE TERMINAL ADDRESS ....................................................................... 14
4.0.0
DATA STRUCTURE ............................................................................................................... 15
4.1.1
ADDRESS MAP ................................................................................................................ 15
4.1.2 INTERNAL REGISTER MAP.................................................................................................. 16
4.2.0
INTERNAL REGISTERS
..................................................................................................... 17
4.2.1
CONTROL
Address: 0
R/ W BC/ MT/ RT................... 17
4.2.2 MESSAGE POINTER TABLE ADDRESS
Address: 1
R/ W
RT........ 18
4.2.3
BASIC STATUS
Address: 2
R/ W
RT .......................... 18
4.2.4
INTERRUPT REQUEST
Address: 3(Ubyte)
W
BC/ MT/ RT ..... 19
4.2.5
INTERRUPT MASK
Address: 3 Lbyte
R/ W BC/ MT/ RT.... 19
4.2.6
INTERRUPT VECTOR
Address: 3(Ubyte)
R
BC/ MT/ RT .... 20
4.2.7
CONFIGURATION REGISTER 2
Address: 4(Ubyte)
W
BC/ MT/ RT ... 20
4.2.8
AUXILIARY VECTOR REGISTER
Address: 4(Ubyte)
R
BC/ MT/ RT.... 21
4.2.9
REAL- TIME CLOCK ....................................................................................................... 21
4.2.10
RTC CONTROL REGISTER
Address: 7
R/ W BC/ MT/ RT......... 22
4.2.11
FIFO READ
Address: 8
R
BC/ MT/ RT.................... 23
4.2.12
FIFO RESET
Address: 8
W
BC/ MT/ RT ................... 23
4.2.13
CONFIGURATION REGISTER 1
Address: 9
R/ W BC/ MT/ RT....... 23
4.2.14
BC FRAME INDEX
Address: 10
R
BC ...... 25
4.2.15
LAST COMMAND REGISTER
Address: 11
R
RT ................................ 25
4.2.16
LAST STATUS REGISTER
Address: 12
R
RT..................................... 25
4.2.17
MAJOR FRAME "A" ADDRESS
Address: 13
R/ W BC ........................... 25
4.2.18
ASYNCHRONOUS MINOR FRAME ADDRESS
Address: 14
R/ W BC.... 25
-
2
-
4.2.19
4.2.20
4.2.21
4.2.22
4.2.23
4.2.24
4.2.25
4.2.26
4.2.27
4.2.28
4.2.29
4.2.30
4.2.31
4.2.32
4.2.33
4.2.34
4.2.35
4.2.36
4.2.37
4.2.38
4.2.39
4.2.40
4.2.41
4.2.42
5.0
RESET REMOTE TERMINAL
Address: 15
W
BC/ MT/ RT .................... 25
MAJOR FRAME "B" ADDRESS
Address: 16
R/ W BC ......................... 25
RESERVED
Address: 17............................................................ 25
ENCODER STATUS
Address: 18
R
BC/ RT .............................. 25
CONDITION REGISTER
Address: 19
R
BC/ MT/ RT .................... 26
MINOR FRAME_ TIME
Address: 20
R/ W
BC ................... 27
CONFIGURATION REGISTER 3
Address: 21
R/ W BC/ MT/RT.......... 28
MT ADDRESS FILTER (15:0)
Address: 22
R/ W MT................ 29
ENCODER DATA REGISTER
Address: 23
R/W
RT ....................... 29
ENCODER DATA TRANSMIT RQST Address: 24
W
RT ...................... 29
ENCODER COMMAND TRANSMIT REQUEST
Address: 25
W
RT ...... 29
MT ADDRESS FILTER (31:16)
Address: 26
R/ W MT............. 30
BLOCK "A" LAST ADDRESS
Address: 27
R
MT ............. 30
CURRENT MINOR FRAME ADDRESS
Address: 27
R
BC...... 30
REGISTER 27 CLEAR
Address: 27
W
BC/MT ....... 30
BLOCK "B" LAST ADDRESS
Address: 28
R
MT ............. 30
CURRENT MESSAGE ADDRESS
Address: 28
R
BC ........... 30
REGISTER 28 CLEAR
Address: 28
W
BC/MT ............ 30
LOG POINTER TABLE ADDRESS
Address: 29
R/W RT ............. 30
EXTERNAL TERMINAL ADDRESS REGISTER
Address: 30 R BC/MT/RT 31
BC/MT INTERRUPT VECTOR
Address: 31
R/ W BC/MT .......... 31
READ- MODIFY- WRITE LOCAL BUS TERMINALS ONLY........................ 32
BUS CONTROLLER FIFO DATA......................................................................... 32
BUS MONITOR FIFO DATA ................................................................................ 32
PCI BUS TERMINALS ONLY.................. 33
PCI CONFIGURATION SPACE REGISTERS
5.1.0 PCI CONFIGURATION SPACE REGISTER MAP
............................................................... 33
5.1.1
PCI BASE ADDRESS........................................................................................................ 33
5.1.2
PCI ADDRESSING AND DATA ..................................................................................... 34
5.1.3
PCI MEMORY ADDRESSING TABLE FOR NHi-156XX TERMINALS...................... 34
5.2.0 PCI COMMANDS
....................................................................................................................... 34
5.2.1 PCI COMMAND TABLE........................................................................................................ 34
6.0.0
MEMORY MANAGEMENT ARCHITECTURE...................................................................... 35
6.1.0
REMOTE TERMINAL MEMORY MANAGEMENT
......................................................... 35
6.1.1
REMOTE TERMINAL MEMORY ORGANIZATION ............................................. 35
6.1.2
MESSAGE POINTER TABLE INDEX............................................................................. 36
6.1.3
MESSAGE POINTER WORD........................................................................................... 36
6.1.4
SUBADDRESS POINTER TABLE CONTROL WORD.............................................. 36
6.1.5
SUBADDRESS POINTER TABLE POINTERS.......................................................... 37
6.1.6
DATA TABLE POINTER WORD ................................................................................. 37
6.1.7.0
REMOTE TERMINAL DATA BUFFERING SCHEME ............................................... 37
6.1.7.1
REMOTE TERMINAL DATA BUFFERING OPERATION........................................ 37
6.1.8
REMOTE TERMINAL DATA TABLE ORGANIZATION ........................................... 39
6.1.9
REMOTE TERMINAL DATA TABLE TAG WORD ...................................................... 39
6.1.10
SAMPLE REMOTE TERMINAL MEMORY MAP ........................................................ 40
6.2.0
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
REMOTE TERMINAL MESSAGE LOG FORMAT ................................................................. 45
LOG POINTER TABLE INDEX ....................................................................................... 45
SUBADDRESS LOG TABLE CONTROL WORD ........................................................... 45
SUBADDRESS LOG TABLE INDEX WORD.................................................................. 46
COMMAND WORD.............................................................................................................. 46
REMOTE TERMINAL LOG TABLE OPERATION......................................................... 46
SAMPLE REMOTE TERMINAL MESSAGE LOG.......................................................... 47
-
3
-
6.3.0
BUS CONTROLLER MEMORY ORGANIZATION ................................................................. 50
6.3.1
MAJOR FRAME................................................................................................................... 53
6.3.2
MINOR FRAME .................................................................................................................. 53
6.3.3 MESSAGE ADDRESS TABLE............................................................................................. 54
6.3.4 BC MESSAGE ....................................................................................................................... 54
6.3.5 BUS CONTROLLER DATA TABLE .................................................................................... 58
6.3.6 ASYNCHRONOUS FRAME................................................................................................... 59
6.3.7 BCU MAJOR FRAME TRIGGER.......................................................................................... 59
6.3.8
BUS CONTROLLER APPLICATIONS............................................................................ 59
6.3.9
SAMPLE BUS CONTROLLER MEMORY MAP .............................................................. 60
6.4.0 MESSAGE MONITOR DATA BLOCKS ..................................................................................... 63
6.4.1 MESSAGE MONITOR MESSAGE BLOCKS...................................................................... 64
MESSAGE MONITOR MESSAGE BLOCK STRUCTURE ................................................................ 64
6.4.2
SAMPLE MESSAGE MONITOR MEMORY MAP.......................................................... 67
6.5.0 WORD MONITOR DATA BLOCKS ........................................................................................... 68
6.5.1 WORD MONITOR WORD BLOCKS................................................................................... 69
6.5.2
SAMPLE WORD MONITOR MEMORY MAP ................................................................. 70
7.0
7.1
8.0.0
8.1.0
8.2.0
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
9.0
9.1
9.2
10.0
SIMULTANEOUS MONITOR AND REMOTE TERMINAL............................................... 71
SIMULTANEOUS MODE INTERRUPT HANDLING............................................................... 71
REMOTE TERMINAL MODE CODE OPERATION........................................................ 72
GENERAL............................................................................................................................... 72
TABLE OF RT MODE CODE RESPONSES .......................................................................... 72
DYNAMIC BUS CONTROL (00000; T/ R= 1)................................................................. 72
SYNCHRONIZE WITHOUT DATA (00001; T/ R= 1) .................................................... 73
TRANSMIT LAST STATUS WORD (00010; T/ R= 1).................................................... 73
INITIATE SELF TEST (00011; T/ R= 1) .......................................................................... 73
TRANSMITTER SHUTDOWN (00100; T/ R= 1)............................................................. 74
OVERRIDE TRANSMITTER SHUTDOWN (00101; T/ R= 1) ....................................... 74
INHIBIT TERMINAL FLAG (00110; T/ R= 1) ................................................................ 74
OVERRIDE INHIBIT TERMINAL FLAG (00111; T/ R= 1) ........................................... 75
RESET REMOTE TERMINAL (01000; T/ R= 1) ............................................................. 75
RESERVED MODE CODES (01001- 01111; T/ R= 1).................................................... 75
TRANSMIT VECTOR WORD (10000; T/ R= 1)............................................................. 76
SYNCHRONIZE WITH DATA WORD (10001; T/ R= 0)............................................... 76
TRANSMIT LAST COMMAND (10010; T/ R= 1).......................................................... 77
TRANSMIT BIT WORD (10011; T/ R= 1) ...................................................................... 77
SELECTED TRANSMITTER SHUTDOWN (10100; T/ R= 0)....................................... 78
OVERRIDE SELECTED TRANSMITTER SHUTDOWN (10101; T/ R= 0).................. 78
RESERVED MODE CODES (10110- 11111; T/ R= 1).................................................... 79
RESERVED MODE CODES (10110- 11111; T/ R= 0).................................................... 79
INITIALIZATION ...................................................................................................................... 79
INTERNAL INITIALIZATION ................................................................................................... 79
HOST INITIALIZATION OF TERMINAL ................................................................................. 80
INTERRUPT HANDLING....................................................................................................... 81
-
4
-
10.1
10.2
11.0
12.0
12.1
12.2.0
12.3
12.4
12.5
12.6
13.0
13.1
13.3
13.4
14.0.0
HARDWARE ACKNOWLEDGE
LOCAL BUS TERMINALS ONLY .................................. 82
SOFTWARE ACKNOWLEDGE.............................................................................................. 82
PC BOARD CONSIDERATIONS AND GUIDE LINES....................................................... 82
PIN FUNCTIONAL DESCRIPTION...................................................................................... 83
GENERAL PURPOSE SIGNALS............................................................................................. 83
HOST INTERFACE SIGNALS – LOCAL BUS TERMINALS ............................................... 83
HOST INTERFACE SIGNALS – PCI BUS TERMINALS .................................................. 84
DISCRETE I/O SIGNALS ........................................................................................................ 84
MIL-BUS INTERFACE SIGNALS ........................................................................................ 85
POWER SIGNALS ................................................................................................................ 85
ELECTRICAL CHARACTERISTICS .................................................................................... 86
ABSOLUTE MAXIMUM RATINGS.......................................................................................... 86
I/O TYPES & DESCRIPTIONS ................................................................................................ 86
I/O ELECTRICAL CHARACTERISTICS.................................................................................. 87
TIMING DIAGRAMS – LOCAL BUS TERMINALS......................................................... 88
14.0.1
HOST WRITE CYCLE – LOCAL BUS TERMINALS.................................................... 88
14.0.2
HOST READ CYCLE – LOCAL BUS TERMINALS ..................................................... 88
14.0.3
HOST READ- MODIFY- WRITE CYCLE – LOCAL BUS TERMINALS .................... 89
14.0.4 HARDWARE INTERRUPT ACKNOWLEDGE CYCLE – LOCAL BUS TERMINALS... 89
14.0.5 TERMINAL ADDRESS READ CYCLE............................................................................. 90
14.0.6 SOFTWARE INTERRUPT ACKNOWKEDGE - LOCAL BUS TERMUNALS ............... 90
14.0.7
TIMING NOTES – LOCAL BUS TERMINALS ............................................................. 91
14.1.0
14.1.1
14.1.2
14.1.3
15.0
TIMING PARAMETER TABLES FOR LOCAL BUS TERMINALS....................................... 91
HOST READ, WRITE, READ- MODIFY- WRITE TABLE and .................................... 91
TERMINAL ADDRESS READ TABLE – LOCAL AND PCI BUS TERMINALS........ 91
HARDWARE INTERRUPT ACKNOWLEDGE CYCLE TABLE................................. 92
PIN FUNCTION TABLE .......................................................................................................... 93
15.1 UNIVERSAL PIN FUNCTIONS 68 PIN QUAD FLAT PACK LOCAL BUS TERMINALS ........ 93
15.2 UNIVERSAL PIN FUNCTIONS 68 PIN QUAD FLAT PACK
PCI BUS TERMINALS............ 94
15.3 UNIVERSAL PIN FUNCTIONS PLASTIC BGA PACKAGE LOCAL BUS TERMINALS .......... 95
15.4 UNIVERSAL PIN FUNCTIONS PLASTIC BGA PACKAGE PCI BUS TERMINALS................ 96
15.5
GENERIC PACKAGE OUTLINE DRAWINGS ........................................................................... 97
15.6 BALL GRID ARRAY PACKAGE
................................................................................................ 97
17.0
18.0
ORDERING INFORMATION................................................................................................ 100
REVISIONS .............................................................................................................................. 104
-
5
-
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
