FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT810BT/CT
FEATURES:
0.5 MICRON CMOS technology
Guaranteed low skew < 600ps (max.)
Very low duty cycle distortion < 700ps (max.)
Low CMOS power levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: –32mA I
OH
, 48mA I
OL
Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
•
•
•
•
•
•
•
•
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
V
CC
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
OB
1
OB
2
OB
3
GND
OB
4
OB
5
GND
OE
B
IN
B
3103 drw 02
OE
A
5
IN
A
OA
1
-OA
5
OA
1
OA
2
OA
3
GND
OE
B
5
IN
B
OB
1
-OB
5
3103 drw 01
OA
4
OA
5
GND
OE
A
IN
A
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
OA
2
OA
1
INDEX
3
OA
3
GND
OA
4
OA
5
GND
4
5
6
7
8
2
1
20 19
18
17
OB
2
OB
3
GND
OB
4
OB
5
L20-2
OB
1
16
15
14
9 10 11 12 13
OE
A
V
CC
IN
B
OE
B
IN
A
V
CC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
GND
3103 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
OCTOBER 1995
DSC-4646/3
9.4
1
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
OE
A
,
OE
B
IN
A
, IN
B
OA
n
,
OB
n
Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
3103 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to V
CC
+0.5
0 to +70
–55 to +125
–55 to +125
–60 to +120
–0.5 to V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
–60 to +120
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max. Unit
6.0
pF
8.0
pF
3103 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
3103 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(5)
Input LOW Current
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Input HIGH Current
(5)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
V
CC
= Min.
I
OL
= 32mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
V
CC
= Max., V
IN
= GND or V
CC
V
CC
= Min.
V
IN
= V
IH
or V
IL
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
–60
2.4
2.0
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
—
150
5
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
–225
—
—
0.55
±1
—
500
V
µA
mV
µA
Unit
V
V
µA
µA
µA
µA
µA
V
mA
V
V
OL
I
OFF
V
H
Output LOW Voltage
Input/Output Power Off Leakage
(5)
Input Hysteresis for all inputs
Quiescent Power Supply Current
I
CCL
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
3103 lnk 04
9.4
2
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
50% Duty Cycle
V
CC
= Max.
Outputs Open
fo= 25MHz
50% Duty Cycle
OE
A
= GND,
OE
B
=V
CC
V
CC
= Max.
Outputs Open
fo = 50MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
2.0
100
Unit
mA
µA/
MHz/bit
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
7.5
13
mA
—
—
7.8
30.0
14.0
50.5
(5)
—
30.5
52.5
(5)
3103 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
9.4
3
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
IDT54/74FCT810BT
Com'l.
Symbol
Parameter
t
PLH
Propagation Delay
IN
A
to OA
n
, IN
B
to
OB
n
t
PHL
t
R
Output Rise Time
t
F
Output Fall Time
t
SK1
(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
t
SK2
(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
t
SK
(p)
t
SK
(t)
Pulse skew: skew between opposite
transitions of same output |(t
PHL
-t
PLH
)|
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Output Enable Time
OE
A
to OA
n
,
OE
B
to
OB
n
Output Disable Time
OE
A
to OA
n
,
OE
B
to
OB
n
Mil.
IDT54/74FCT810CT
Com'l.
Mil.
Unit
ns
ns
ns
ns
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min
.(2)
Max.
C
L
= 50pF
1.5
4.5
1.5
4.9
1.5
4.3
1.5
4.6
R
L
= 500Ω
—
1.5
—
2.0
—
1.5
—
2.0
—
—
1.5
0.5
—
—
1.5
0.9
—
—
1.5
0.3
—
—
1.5
0.7
—
0.7
—
1.1
—
0.6
—
1.0
ns
—
—
0.7
1.2
—
—
1.2
1.5
—
—
0.7
1.0
—
—
1.1
1.2
ns
ns
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5
1.5
6.0
6.0
1.5
1.5
6.5
6.5
1.5
1.5
5.0
5.0
1.5
1.5
6.0
6.0
ns
ns
3103 tbl 06
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.4
4
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
3103 drw 04
ENABLE AND DISABLE TIME
SWITCH POSITION
7.0V
V
OUT
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
Open
500Ω
3103 lnk 07
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
TEST WAVEFORMS
PACKAGE DELAY
3V
1.5V
INPUT
t
PLH
t
PHL
2.0V
OUTPUT
t
R
t
F
3103 drw 05
OUTPUT SKEW (SAME BANK) - t
SK1
(o)
INPUT
t
PLH1
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
0V
V
OH
1.5V
0.8V
V
OL
OUTPUT 2
OUTPUT 1
t
SK1(o)
t
SK1(o)
t
PLH2
t
PHL2
3103 drw 06
t
SK1(o)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PLH1
|
OUTPUT SKEW (ALL BANKS) - t
SK2
(o)
INPUT
3V
1.5V
0V
V
OH
1.5V
V
OL
t
SK2(o)
OUTPUT 2
t
PHL2
t
PLH2
3103 drw 07
PULSE SKEW - t
SK
(p)
INPUT
t
PLH
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
t
SK(p)
= |t
PHL -
t
PLH
|
3103 drw 08
t
PLH1
t
PHL1
OUTPUT 1
t
SK2(o)
V
OH
1.5V
V
OL
OUTPUT
t
SK2(o)
= |t
PHL2 -
t
PLH1
|
or
|t
PLH2 -
t
PHL1
|
PACKAGE SKEW - t
SK
(t)
INPUT
t
PD1a
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
PD2a
t
PD2b
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
1.5V
0V
3.5V
1.5V
0.3V
t
PHZ
0.3V
V
OH
0V
3103 drw 10
DISABLE
3V
1.5V
0V
t
PLZ
3.5V
V
OL
t
PD1b
PACKAGE 1 OUTPUT
t
SK2(o)
PACKAGE 2 OUTPUT
t
SK2(o)
t
SK(t)
= |t
PD2a -
t
PD1a
|
or
|t
PD2b-
t
PD1b
|
Package 1 and Package 2 are same device type and speed grade
3103 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
9.4
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
