FAST CMOS
1-TO-10
CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT807BT/CT
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Guaranteed low skew < 250ps (max.)
Very low duty cycle distortion < 350ps (max.)
High speed: propagation delay < 2.5ns (max.)
100MHz operation
TTL compatible inputs and outputs
TTL level output voltage swings
1:10 fanout
Output rise and fall time < 1.5ns (max.)
Low input capacitance: 4.5pF typical
High Drive: -32mA I
OH
, 48mA I
OL
ESD > 2000V per MIL STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT807BT/CT clock driver is built using
advanced dual metal CMOS technology. This low skew clock
driver features 1:10 fanout, providing minimal loading on the
preceding drivers. The IDT54/74FCT807BT/CT offers low
capacitance inputs with hysteresis for improved noise margins.
TTL level outputs and multiple power and grounds reduce
noise. The device also features -32/48mA drive capability for
driving low impedance traces.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
IN
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
3017 drw 02
O
1
O
2
GND
O
1
VCC
O
3
O
4
O
2
GND
O
3
O
5
IN
O
6
VCC
O
4
GND
O
7
O
8
O
9
O
10
V
CC
3017 drw 01
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
GND
V
CC
O
1
INDEX
3
4
5
6
7
8
O
2
GND
O
3
V
CC
2
1
20 19
18
17
O
9
GND
O
8
V
CC
O
7
L20-2
O
10
16
15
14
9 10 11 12 13
O
4
O
5
IN
GND
O
6
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
GND
3017 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
OCTOBER 1995
DSC-4242/3
9.3
1
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
IN
Ox
Description
Input
Outputs
3017 tbl 01
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max. Unit
6.0
pF
8.0
pF
3017 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to V
CC
+0.5
0 to +70
–55 to +125
–55 to +125
–60 to +120
–0.5 to V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
–60 to +120
V
°C
°C
°C
mA
3017 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability. No terminal voltage may exceed V
CC
by
+0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Output and I/O terminals.
9.3
2
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(5)
Input LOW Current
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Input HIGH Current
(5)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
V
CC
= Min.
I
OL
= 32mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
V
CC
= Max., V
IN
= GND or V
CC
V
CC
= Min.
V
IN
= V
IH
or V
IL
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
–60
2.4
2.0
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
—
150
5
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
–225
—
—
0.55
±1
—
500
V
µA
mV
µA
Unit
V
V
µA
µA
µA
µA
µA
V
mA
V
V
OL
I
OFF
V
H
Output LOW Voltage
Input/Output Power Off Leakage
(5)
Input Hysteresis for all inputs
Quiescent Power Supply Current
I
CCL
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
3017 lnk 04
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(3)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
V
CC
= Max.
Input toggling
50% Duty Cycle
Outputs Open
V
CC
= Max.
Input toggling
50% Duty Cycle
Outputs Open
fi = 50MHz
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
0.4
Max.
2.0
0.6
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(5)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
20.0
30.5
(4)
mA
—
20.3
31.3
(4)
3017 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
i
)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
i
= Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
9.3
3
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
IDT54/74FCT807BT
Com'l.
Symbol
Parameter
t
PLH
Propagation Delay
t
PHL
t
R
Output Rise Time
t
F
t
SK
(o)
t
SK
(p)
t
SK
(t)
Output Fall Time
Output skew: skew between outputs of
same package (same transition)
Pulse skew: skew between opposite
transitions of same output (|t
PHL -–
t
PLH
|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Conditions
(1)
50Ω to V
CC
/2,
C
L
= 10pF
(See figure 1)
or 50Ω ac
termination,
C
L
= 10pF
(See figure 2)
f
≤
100MHz
Outputs
connected in
groups of two
Min.(2)
Max.
IDT54/74FCT807CT
Com'l.
Min.(2)
Max.
Mil.
Min.(2)
Max.
Mil.
Min.(2)
Max.
1.3
—
—
—
—
—
2.7
1.5
1.5
0.5
0.5
0.9
—
—
—
—
—
1.3
—
—
—
—
—
2.5
1.5
1.5
0.25
0.35
0.65
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
3017 tbl 06
IDT54/74FCT807BT
Com'l.
Symbol
Parameter
t
PLH
Propagation Delay
t
PHL
t
R
Output Rise Time
t
F
t
SK
(o)
t
SK
(p)
t
SK
(t)
Output Fall Time
Output skew: skew between outputs of
same package (same transition)
Pulse skew: skew between opposite
transitions of same output (|t
PHL -–
t
PLH
|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Conditions
(1)
C
L
= 30pF
f
≤
67MHz
(See figure 3)
Min.(2)
Max.
IDT54/74FCT807CT
Com'l.
Min.(2)
Max.
Mil.
Min.(2)
Max.
Mil.
Min.(2)
Max.
1.5
—
—
—
—
—
3.8
1.5
1.5
0.5
0.5
0.9
—
—
—
—
—
1.5
—
—
—
—
—
3.5
1.5
1.5
0.25
0.35
0.75
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
3017 tbl 07
IDT54/74FCT807BT
Com'l.
Symbol
Parameter
t
PLH
Propagation Delay
t
PHL
t
R
Output Rise Time
t
F
t
SK
(o)
t
SK
(p)
t
SK
(t)
Output Fall Time
Output skew: skew between outputs of
same package (same transition)
Pulse skew: skew between opposite
transitions of same output (|t
PHL -–
t
PLH
|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Conditions
(1)
C
L
= 50pF
f
≤
40MHz
(See figure 4)
Min.(2)
Max.
IDT54/74FCT807CT
Com'l.
Min.(2)
Max.
Mil.
Min.(2)
Max.
Mil.
Min.(2)
Max.
1.5
—
—
—
—
—
3.8
1.5
1.5
0.5
0.60
1.0
—
—
—
—
—
1.5
—
—
—
—
—
3.5
1.5
1.5
0.35
0.45
0.75
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
3017 tbl 08
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.3
4
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS
50Ω TO V
CC
/2, C
L
= 10pF
V
CC
V
CC
100
Ω
V
IN
Pulse
Generator
R
T
D.U.T.
100
Ω
10pF
R
T
220pF
3017 drw 04
3017 drw 05
50Ω AC TERMINATION, C
L
= 10pF
V
CC
V
OUT
Pulse
Generator
V
IN
D.U.T.
V
OUT
50
Ω
10pF
Figure 1.
The capacitor value for ac termination is determined by the operating
frequency. For very low frequencies a higher capacitor value should be
selected.
Figure 2.
C
L
= 30pF CIRCUIT
V
CC
C
L
= 50pF CIRCUIT
V
CC
V
IN
Pulse
Generator
R
T
D.U.T.
V
OUT
Pulse
Generator
30pF
C
L
3017 drw 06
V
IN
D.U.T.
V
OUT
50pF
R
T
C
L
3017 drw 07
Figure 3.
Figure 4.
ENABLE AND DISABLE TIME CIRCUIT
V
CC
500
Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
3017 drw 08
ENABLE AND DISABLE TIME
SWITCH POSITION
7.0V
V
OUT
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
Open
500
Ω
3017 lnk 09
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Figure 5.
9.3
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
