MA28140
MA28140
Packet Telecommand Decoder
Replaces June 2000 version, DS3839-6.1
DS3839-7.0 September 2001
Coding Layer
Transfer Layer
Segmentation Layer
Authentication Layer
Command Pulse Distribution
Some of these layers have a telemetry reporting
mechanism. The processed TC segment can be transferred to
the application either serially or in parallel.
Parallel
Interface
PRDY
PBUS(0-15)
AUDIS
AUEXT
AUST
AUBUF
AUEND
AUR
AUTSL
AUSBUF
FARBUF
TCC0-5
TCS0-5
TCA0-5
VDD
GND
PTD
LADR(0-10)
LDAT(0-7)
RWN
BRQN
BGRN
RAMCSN
ROMCSN
LACCS
LACK
CPDUSTN
CPDUEN
CPDUDIV
MAPSTN
MAPCK
MAPDSR
MAPDTR
MAPDATA
MAPADT
123 144424443
142443
CLCWSA
CLCWCA
CLCWDA
CLCWSB
CLCWCB
CLCWDB
CPDUS
FAR1S
FAR2S
AU1S
AU2S
TMC
TMD
RFAVN
VCLSB
TMMOD
PAR
RESETN
CLK
PRIOR
TEST
MODE
CONF
SELTC(0-2)
DECOD
144444244443
The MA28140 Packet Telecommand Decoder (PTD) is a
single-chip implementation of the core part of a telecommand
decoder, manufactured using CMOS-SOS high performance,
radiation hard, 1.5µm technology. The PTD is a full
implementation of and fully compliant with the packet
telecommand standard ESA PSS-04-107 and the
telecommand decoder specification ESA PSS-04-151, these
being derived from the corresponding CCSDS standards.
The PTD, which handles 6 NRZ TC input channels,
processes the following layers:
1444442444443 123 144424443 123 123
Miscellaneous
Telemetry
Interface
Authentication
Interface
Local Bus
Interface
CPDU
Interface
FEATURES
s
Single Chip Implementation of all TC Decoder Core
Functions
s
Built-in Authentication Unit
s
Built-in Command Pulse Distribution Unit Core Logic
s
Radiation Hard to 1MRads (Si)
s
High SEU Immunity, Latch-up Free
s
CMOS-SOS Technology
s
Conforms to CCSDS Standards
s
6 NRZ TC Input Channels
s
50Kbps Bit Rate
s
Low Power Consumption
s
Single 5V Supply
s
-55 to +125°C Operation
Trans- Power
ponder
Interface
MAP
Interface
12
14
Pin connections
1/72
MA28140
CONTENTS
Page
Front sheet ............................................................................ 1
1. Introduction ....................................................................... 2
2. TC Decoder Subsystem Overview .................................... 3
3. PTD Architectural Overview .............................................. 4
4. PTD Functional Description
4.1 Coding Layer ....................................................... 6
4.2 Transfer Layer ..................................................... 9
4.3 Authentication Layer .......................................... 15
4.4 Segmentation Layer ........................................... 21
4.5 CPDU ................................................................. 22
4.6 Telemetry Reporting .......................................... 24
5. PTD Interfaces
5.1 Physical Channel Interface ................................ 27
5.2 MAP Interface .................................................... 27
5.3 Telemetry Interface ............................................ 30
5.4 Parallel Interface ................................................ 34
5.5 CPDU Interface .................................................. 35
5.6 Local Bus Interface ............................................ 36
5.7 Memories ........................................................... 36
5.8 External Authentication ...................................... 41
6. State After Reset ............................................................. 42
7. Signal Description ........................................................... 44
8. Electrical Characteristics and Ratings
8.1 DC Parameters .................................................. 47
8.2 AC Parameters .................................................. 48
9. Package Details
9.1 Dimensions ........................................................ 65
9.2 Pin Assignment .................................................. 66
10. Radiation Tolerance ...................................................... 70
11. Ordering Information ..................................................... 70
12. Synonyms ..................................................................... 71
1. INTRODUCTION
This document is the data sheet of the “Packet
Telecommand Decoder”, henceforth called the PTD.
The PTD is compatible with the ESA PSS-04-107 standard
directly derived from the CCSDS recommendations. This
standard is described in references 1 and 2. The data sheet is
based on both documents for the description of the protocol.
Nevertheless, it was impossible to include the whole reference
documents in the data sheet, thus some specific points of the
protocol or some descriptions of the recommended hardware
implementation have not been included. The reader may find
these points in the applicable documents.
CONVENTION
In this document the two conventions described in
references 1 and 2 apply:
1. The first bit in the field to be transmitted (i.e. the most left
justified bit when drawing a figure) is defined to be Bit 0. When
the field is used to express a binary value, the Most Significant
Bit (MSB) shall be the first transmitted bit of the field (i.e. Bit 0).
Bit 0
N Bit Data Field
MSB
←
First Bit transmitted = MSB
LSB
Bit N-1
Note: Some of the external interfaces have parallel busses
(LADR, LDAT, PBUS, SELTC) which have the opposite bit
order specified, i.e. Bit 0 is The Least Significant Bit.
2. An 8-bit word (a byte) is called an OCTET.
REFERENCES
1. “Packet Telecommand Standard” ESA PSS-04-107,
Issue 2, April 92.
2. “Telecommand Decoder Specification” ESA PSS-04-151,
Issue 1, September 93.
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MA28140
Local Bus
ROM
External
Authentication
Unit
Configuration
Authentication
RAM
Back-up
Power
Supply
TC input
NRZ or PSK
(6 max)
Transponder
I/F
PTD
CPDU
I/F
Command
Pulses
(256 max)
Serial
Data link
(62 max)
Clock
MAP
Demultiplexer
I/F
Telemetry
I/F
Figure 1: Block Diagram of a TC Decoder Subsystem
2. TC DECODER SUBSYSTEM OVERVIEW
An ESA/CCSDS Telecommand Decoder subsystem
including the PTD and fulfilling the receiving-end functions
established in the Packet Telecommand Standard (ref 1) is
shown in Figure 1.
The PTD requires the following additional hardware to fulfil
the requirements of the Telecommand Decoder Specification
(ref 2):
• Transponder I/F including demodulators for PSK TC
inputs.
• Telemetry I/F. The telemetry reporting signals can be
directly connected to a Virtual Channel Multiplexer (ref 3).
• Command Pulse Distribution Unit I/F. This function
performs decoding of commands present on the local bus
and power amplification. The PTD ASIC associated with
the CPDU I/F can manage 256 pulse outputs.
• MAP demultiplexer I/F. This interface is composed of a
demultiplexer to provide the TC segment data to various
Data Management System interfaces. The demultiplexer
is controlled by the MAP data present on the Local Bus.
The PTD ASIC can manage 62 different serial data
interfaces (63 if AU is disabled).
• Memories. There are 2 different memories:
- RAM (2Kx8) used to store the received TC data and
protocol variables (programme authentication key for
instance) and eventually to store the TC segment
available for further processing by the Data Management
System. If this memory is used to store the recovery LAC
counter (Authentication function), it must be a non-volatile
memory.
- ROM (1Kx8) divided in two parts:
- Configuration part, used to provide the Mission
Specific Data.
- Authentication part, used to provide the fixed
Authentication key.
• External Authentication Unit (optional). Although an AU is
implemented in the PTD, it is also possible to use an
external AU if the mission requires a different
authentication algorithm. This external unit accesses the
RAM in order to authenticate a TC segment.
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MA28140
3. PTD ARCHITECTURAL OVERVIEW
Figure 2 describes the PTD functional architecture which
features 7 major blocks described below. Figure 3 shows the
CCSDS protocol layer architecture. The PTD deals with the
Coding Layer, the Transfer Layer, the Authentication Layer,
the Segmentation Layer and a part of the Packetisation Layer
of the CCSDS protocol.
AUTHENTICATION UNIT BLOCK
This block (which is optional and can be disabled
permanently or during flight) is concerned with the segment
data protection, it enables the spacecraft to authenticate the
received data. The authentication concept is the “plain text
with appended signature” approach, described in Section 8 of
ref. 2.
In the PTD architecture this function is implemented on
chip. However, a specific interface allows authentication to be
performed externally - if another coding algorithm is to be
used, the on-chip block can be disabled and an external
authentication system can be used.
The block generates a reporting word (Authentication
Status = 80 bits) and part of the 32 bit FAR.
CODING LAYER BLOCK
The coding layer block multiplexes the 6 physical TC
channel inputs and fulfils the coding layer function described in
section 5 of ref.1.
The main tasks performed by the PTD at this level are:
• Start sequence detection and selection of the first active
TC input.
• Codeblock error detection and correction.
• Valid codeblock transfer to the above layer.
• Generation of part of the FAR and CLCW status.
SEGMENTATION LAYER BLOCK
This block implements only some of the segmentation
layer functions described in section 7 of ref.1. Its purpose is to
manage the back-end buffer shared with the FARM-1 block of
the transfer layer and to implement the MAP interface in order
to demultiplex (with external hardware) the segments
dedicated to the different spacecraft applications.
TRANSFER LAYER BLOCK
This level is concerned with the processing of the frames
received from the coding layer and fulfils the transfer layer
function described in section 6 of ref.1.
At this level, the PTD performs the following tasks:
• Clean frame validation.
• Legal frame validation.
• Frame analysis report mechanism.
• Reporting word (16 bit CLCW and part of 32 bit FAR)
generation.
6447448
DATA CTL
8
AD
FAR28...30 AUS0...79
11
CLCW
CPDUS
BUS
CONTROLLER
AUTHENTICATION
UNIT
FAR
AUS
TELEMETRY
MODULE
TM interface
EXTERNAL BUS
adr
control
data
INTERNAL BUS
CLK
DATA
ACTIVE
6
6
6
CODING LAYER
BLOCK
CLEAN FRAME
VALIDATION
BLOCK
TRANSFER LAYER
LEGAL FRAME
VALIDATION
BLOCK
FARM-1
BLOCK
SEGMENTATION
LAYER BLOCK
COMMAND PULSE
DISTRIBUTION
UNIT
FAR7...12
FAR13...15
FAR18...20
FAR1...3
FAR4...6
FAR16,17
FAR1...3
CLCW0...15
FAR21...26
CPDUS0...15
MAP interface
Figure 2: PTD Internal Architecture
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MA28140
EXAMPLE : 256 OCTETS
PACKETISATION
LAYER
PACKET
HEADER
PACKET
DATA
PACKET
ERROR
CONTROL
1 OCTET
SEGMENTATION
LAYER
SEGMENT
HEADER
248 OCTETS
FIRST PACKET
SEGMENT
1
SEGMENT
HEADER
8
LAST PACKET
SEGMENT
5
TRANSFER
LAYER
FRAME
HEADER
249 (MAX.)
FRAME DATA
FIELD
2
FRAME
ERROR
CONTROL
5
9
2
FRAME
FRAME FRAME DATA
ERROR
HEADER
FIELD
CONTROL
2
CODING
LAYER
(CODEBLOCK
LENGTH = 8
OCTETS)
START
SEQUENCE
7
INFOR-
MATION
1
ERROR
CONTROL
7
1
E.C.
1
E.C.
7
1
E.C.
4
3
FILL
1
8
TAIL
E.C.
SEQUENCE
CODEBLOCK
No.1
CODEBLOCK
No.2
CODEBLOCK
No.36
CODEBLOCK
No.37
16 OCTETS
PHYSICAL
LAYER
(ESA PLOP-2)
ACQUISITION
SEQUENCE
306 OCTETS
FIRST CLTU
MIN. 1 OCTET
IDLE SEQUENCE
34 OCTETS
LAST CLTU
IDLE SEQUENCE
(OPTIONAL)
F
igure 3: CCSDS Protocol Layer Architecture
COMMAND PULSE DISTRIBUTION UNIT
The CPDU is integrated into the PTD ensuring higher
reliability for this critical function (direct telecommand for
spacecraft reconfiguration) than if implemented in an external
chip. The critical commands executed by the CPDU are
received in specific packets. The CPDU responds to the MAP
identifier 0, and to a mission dependent application process
identifier (stored in ROM). No segmentation is accepted, the
commands must be contained in an unsegmented package.
The unit generates a reporting word (CPDU Status = 16 bits).
BUS CONTROLLER
This block is the interface between external memories and
on chip modules. Its different functions are:
• address decoding.
• internal and external bus access arbitration.
TELEMETRY MODULE
This block is the interface with the telemetry subsystem. It
manages the data report storage using double buffered
registers.
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