FAST CMOS OCTAL
TRANSCEIVER/
REGISTERS (3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT
IDT54/74FCT648T/AT/CT
IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT
FEATURES:
• Common features:
– Low input and output leakage
≤1µA
(max.)
– Extended commercial range of –40°C to +85°C
– CMOS power levels
– True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, TSSOP,
CERPACK and LCC packages
• Features for FCT646T/648T/652T:
– Std., A, C and D speed grades
– High drive outputs (-15mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
• Features for FCT2646T/2652T:
– Std., A, and C speed grades
– Resistor outputs (-15mA I
OH
, 12mA I
OL
Com.)
(-12mA I
OH
, 12mA I
OL
Mil.)
– Reduced system switching noise
DESCRIPTION:
The FCT646T/FCT2646T/FCT648T/FCT652T/2652T con-
sist of a bus transceiver with 3-state D-type flip-flops and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage regis-
ters.
The FCT652T/FCT2652T utilize GAB and
GBA
signals to
control the transceiver functions. The FCT646T/FCT2646T/
FCT648T utilize the enable control (
G
) and direction (DIR)
pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real-
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-
time data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (CPAB or CPBA), regardless of the select or
enable control pins.
The FCT26xxT have balanced drive outputs with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
IDT54/74FCT652/2652
ONLY
GBA
GAB
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT646/2646/648
ONLY
G
DIR
CPBA
SBA
CPAB
SAB
B REG
1 OF 8 CHANNELS
1D
C1
646/2646/652/2652
ONLY
A1
A REG
1D
C1
B1
646/2646/652/2652
ONLY
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2634 drw 01
TO 7 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2634/9
6.20
1
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CPAB
NC
V
CC
GND
NC
B
8
A
7
A
8
B
7
B
6
CPAB
SAB
DIR
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
SO24-9*
&
E24-1
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
DIR
G
FCT646/FCT2646T
FCT648
A
1
A
2
A
3
NC
A
4
A
5
A
6
5
6
7
8
9
4
SAB
INDEX
3 2 1 28 27 26
25
24
23
L28-1
22
21
CPBA
SBA
PIN CONFIGURATIONS
G
B
1
B
2
NC
B
3
B
4
B
5
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
2634 drw 02
10
20
1112 13 14 15 16 17 1819
2634 drw 03
DIP/SOIC/SSOP/
QSOP/TSSOP/CERPACK
TOP VIEW
* FCT646/2646T/AT/CT/DT only
LCC
TOP VIEW
GAB
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
&
E24-1
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
FCT652/FCT2652T
A
1
A
2
A
3
NC
A
4
A
5
A
6
5
6
7
8
GBA
4
SAB
INDEX
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
2634 drw 04
3 2 1 28 27 26
25
24
23
L28-1
CPAB
NC
V
CC
CPBA
SBA
GBA
B
1
B
2
NC
B
3
B
4
B
5
2634 drw 05
22
21
9
10
20
19
11
12 13 14 15 16 17 18
GND
NC
B
8
A
7
A
8
B
7
B
6
DIP/SOIC/SSOP/
QSOP/CERPACK
TOP VIEW
* FCT652/2652T/AT/CT/DT only
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
A
1
- A
8
B
1
- B
8
CPAB, CPBA
SAB, SBA
GAB,
GBA
DIR,
G
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs (646/648)
Output Enable Inputs (652)
2634 tbl 01
6.20
2
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (646/648)
Inputs
Data I/O
(1)
SAB
X
X
X
X
L
H
SBA
X
X
L
H
X
X
A
1
- A
8
Input
Output
Input
B
1
- B
8
Input
Input
Output
Operation or Function
FCT646T/FCT2646T
Isolation
Store A and B Data
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
FCT648T
Isolation
Store A and B Data
Real-Time
B
Data to A Bus
Stored
B
Data to A Bus
Real-Time
A
Data to B Bus
Stored
A
Data to B Bus
2634 tbl 02
G
H
H
L
L
L
L
DIR
X
X
L
L
H
H
CPAB
H or L
↑
X
X
X
H or L
CPBA
H or L
↑
X
H or L
X
X
FUNCTION TABLE (652)
Inputs
GAB
L
L
X
H
L
L
L
L
H
H
H
Data I/O
SAB
X
X
X
X
(2)
X
X
X
X
L
H
H
SBA
X
X
X
X
X
X
(2)
L
H
X
X
H
A
1
- A
8
Input
Input
Input
Unspecified
(1)
Output
Output
Input
Output
B
1
- B
8
Input
Operation or Function
FCT652T/FCT2652T
Isolation
Store A and B Data
GBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
Unspecified
(1)
Store A, Hold B
Output
Store A in Both Registers
Input
Input
Input
Output
Output
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and Stored B Data to A Bus
2634 tbl 03
NOTES:
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = HIGH, L = LOW, X = Don't Care,
≠
= LOW-to-HIGH transition.
3.
A
in B Register.
4.
B
in A Register.
6.20
3
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
GAB
L
646/2646/ DIR
648
L
652/2652
GBA
L
G
L
CPAB
X
CPAB
X
CPBA
X
CPBA
X
SAB
X
SAB
X
SBA
L
SBA
L
652/2652
646/2646/
648
GAB
H
DIR
H
GBA
H
G
L
CPAB
X
CPAB
X
CPBA
X
CPBA
X
SAB
L
SAB
L
SBA
X
SBA
X
REAL-TIME TRANSFER
BUS B TO A
2634 drw 06
REAL-TIME TRANSFER
BUS A TO B
2634 drw 07
BUS
A
BUS
B
BUS
A
BUS
B
652/2652
GAB
X
L
L
DIR
H
L
X
GBA
H
X
H
G
L
L
H
CPAB
↑
X
↑
CPAB
↑
X
↑
CPBA
X
↑
↑
CPBA
X
↑
↑
SAB
X
X
X
SAB
X
X
X
SBA
X
X
X
SBA
X
X
X
652/2652
GAB
H
(1)
GBA
L
G
L
L
CPAB
H or
CPAB
X
H or
CPBA
H or
CPBA
H or
X
SAB
H
SAB
X
H
SBA
H
SBA
H
X
646/2646/
648
646/2646/
648
DIR
L
H
TRANSFER STORES
DATA TO A AND/OR B
2634 drw 09
STORAGE FROM
A AND/OR B
NOTE:
1. 646/2646/648 cannot transfer data to A bus and B bus simultaneously.
2634 drw 08
6.20
4
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
(2)
Terminal Voltage with Respect to –0.5 to +7.0
V
TERM
GND
V
TERM(3)
Terminal Voltage with Respect to
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2634 lnk 05
°
C
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2634 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
Unit
V
V
µA
µA
µA
V
mV
mA
2634 lnk 05
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR FCT646T/648T/652T
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 48mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 64mA COM'L.
V
CC
= Max., V
O
= GND
(3)
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2.0
—
–60
—
Typ.
(2)
3.3
3.0
0.3
–120
—
Max.
—
—
0.55
–225
±1
Unit
V
V
V
mA
µA
2634 lnk 06
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
6.20
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
