IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
FAST CMOS OCTAL
BUS TRANSCEIVERS
(3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT623T/AT/CT
FEATURES:
•
•
•
•
Std., A and C speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, CERPACK and LCC packages
DESCRIPTION
The FCT623T/AT/CT is a non-inverting octal transceiver
with 3-state bus-driving outputs in both the send and receive
directions. The B bus outputs are capable of sinking 64mA and
sourcing up to 15mA, providing very good capacitive drive
characteristics.
These octal bus transceivers are designed for asynchro-
nous two-way communication between data buses. The control
function implementation allows for maximum flexibility in
timing.
One important feature of the FCT623T/AT/CT is the Power
Down Disable capability. When the GAB and
G
BA inputs are
conditioned to put the device in high-Z state, the I/O ports will
maintain high impedance during power supply ramps and
when V
CC
= 0V. This is a desirable feature in back-plane
applications where it may be necessary to perform “live”
insertion and removal of cards for on-line maintenance. It is
also a benefit in systems with multiple redundancy where one
or more redundant cards may be powered-off.
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
GBA
GAB
A1
B1
A2 - A8
B2 - B8
7 other transceivers
2563 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
NOVEMBER 1995
DSC-2563/5
6.19
6.19
1
1
IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
GAB
1
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
2
3
4
5
6
7
8
9
10
19
18
P20-1
D20-1 16
SO20-2 15
&
E20-1 14
13
12
11
17
GBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
2563 drw 02
A
2
3
A
3
A
4
A
5
A
6
A
7
4
5
6
7
8
A
1
1
20
V
CC
2
20 19
18
17
16
15
14
GBA
V
CC
INDEX
B
1
B
2
B
3
B
4
B
5
L20-2
9 10 11 12 13
GND
B
8
B
7
A
8
B
6
DIP/SOIC/CERPACK
TOP VIEW
2563 drw 03
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
Pin Names
G
BA, GAB
A
1
- A
8
B
1
- B
8
Description
Enable Inputs
A Bus Inputs or 3-State Outputs
B Bus Inputs or 3-State Outputs
2563 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
(3)
Terminal Voltage
V
TERM
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
FUNCTION TABLE
(1)
°
C
°
C
°
C
W
mA
G
BA
L
H
H
L
Enable Inputs
GAB
L
H
L
H
Outputs
B data to A bus
A data to B bus
Z
B data to A bus
A data to B bus
2563 tbl 02
NOTES:
1. H = HIGH Voltage Level
2. L = LOW Volage Level
3. Z = High-Impedance (OFF) state
2563 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(
T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2563 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
6.19
2
IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(5)
Input LOW Current
(5)
Input HIGH Current
(5)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
(A and B Bus)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
I
= 2.7V
V
CC
= Max., V
I
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
I
OH
= –6mA MIL.
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 32mA MIL.
(4)
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
V
CC
= Min.
I
OL
= 48mA MIL.
(4)
V
IN
= V
IH
or V
IL
I
OL
= 64mA COM'L.
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
Min.
2.0
—
—
—
—
—
–60
2.4
2.0
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
0.3
—
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
0.55
±1
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
V
V
µA
mV
µA
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
V
OL
I
OFF
V
H
I
CC
Output LOW Voltage (A Bus)
Output LOW Voltage (B Bus)
Input/Output Power Off Leakage
(6)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
IN
=
GND or V
CC
NOTES:
2563 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These are maximum I
OL
values per output, for 8 outputs turned on simultaneously. Total maximum I
OL
(all outputs) is 512mA for commercial and 384mA
for military. Derate I
OL
for number of outputs exceeding 8 turned on simultaneously.
5. The test limit for this parameter is
±5µA
at T
A
= –55°C.
6. This parameter is guaranteed but not tested.
6.19
3
IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
G
BA = GAB = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
G
BA = GAB = GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
G
BA = GAB = GND
Eight Bits Toggling
Min.
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
V
IN
= V
CC
V
IN
= GND
—
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.5
3.5
mA
—
1.8
4.5
—
3.0
6.0
(5)
—
5.0
14.0
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2563 tbl 07
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT623T
Com'l.
Symbol
Parameter
Condition
(1)
Mil.
54/74FCT623AT
Com'l.
Mil.
54/74FCT623CT
Com'l.
Mil.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
An to Bn
Propagation Delay
Bn to An
Output Enable Time
G
BA to An
Output Disable Time
G
BA to An
Output Enable Time
GAB to Bn
Output Disable Time
GAB to Bn
C
L
= 50pF
R
L
= 500Ω
1.5
1.5
1.5
1.5
1.5
1.5
7.5
7.5
9.0
8.0
9.0
8.0
1.5
1.5
9.0
9.5
1.5
1.5
1.5
1.5
1.5
1.5
5.5
5.5
7.0
6.5
7.0
6.5
1.5
1.5
1.5
1.5
1.5
1.5
6.3
6.3
8.0
7.4
8.0
7.4
1.5
1.5
1.5
1.5
1.5
1.5
4.8
4.8
6.1
5.6
6.1
5.6
1.5
1.5
1.5
1.5
1.5
1.5
5.4
5.4
6.9
6.4
6.9
6.4
ns
ns
ns
ns
ns
ns
1.5 10.0
1.5
9.0
1.5 10.5
1.5
9.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays
2563 tbl 07
6.19
4
IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
2563 drw 05
SWITCH POSITION
Test
7.0V
Switch
Open Drain
Disable Low
Enable Low
All Other Tests
Closed
V
OUT
Open
500
Ω
2563 lnk 09
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2563 drw 06
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
t
REM
1.5V
2563 drw 07
t
SU
t
H
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3.5V
0.3V
t
PHZ
0.3V
1.5V
0V
V
OH
0V
2563 drw 09
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
2563 drw 08
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
t
PLZ
V
OL
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
6.19
5
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