®
FAST CMOS OCTAL D
REGISTERS (3-STATE)
IDT54/74FCT374/A/C
IDT54/74FCT534/A/C
IDT54/74FCT574/A/C
Integrated Device Technology, Inc.
FEATURES:
• IDT54/74FCT374/534/574 equivalent to FAST™ speed
and drive
• IDT54/74FCT374A/534A/574A up to 30% faster than
FAST
• IDT54/74FCT374C/534C/574C up to 50% faster than
FAST
• I
OL
= 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common three-
state control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
DESCRIPTION:
The IDT54/74FCT374/A/C, IDT54/74FCT534/A/C and
IDT54/74FCT574/A/C are 8-bit registers built using an ad-
vanced dual metal CMOS technology. These registers consist
of eight D-type flip-flops with a buffered common clock and
buffered 3-state output control. When the output enable (
OE
)
is LOW, the eight outputs are enabled. When the
OE
input is
HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the O outputs on the LOW-to-
HIGH transition of the clock input.
The IDT54/74FCT374/A/C and IDT54/74FCT574/A/ C have
non-inverting outputs with respect to the data at the D inputs.
The IDT54/74FCT534/A/C have inverting outputs.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574
D
0
CP
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2603 cnv* 01
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
D
0
CP
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2603 cnv* 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4622/2
7.13
1
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT374
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
D
0
3
2
3
4
5
6
7
8
9
10
19
18
P20-1 17
D20-1 16
SO20-2 15
&
E20-1 14
13
12
11
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
2603 cnv* 03
O
0
2
1
20
V
CC
OE
V
CC
O
7
1
20 19
18
17
16
15
14
INDEX
D
1
O
1
O
2
D
2
D
3
4
5
6
7
8
D
7
D
6
O
6
O
5
D
5
L20-2
9 10 11 12 13
GND
CP
O
3
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
&
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CP
2603 cnv* 05
3 2
D
2
D
3
D
4
D
5
D
6
4
5
6
7
8
D
0
OE
1
2 1
1
1
1
1
1
O
1
O
2
O
3
O
4
O
5
L20-2
9 1 1 1 1
D
7
GND
CP
O
7
O
6
V
CC
O
0
IDT54/74FCT574
D
1
INDEX
O
4
D
4
2603 cnv* 04
2603 cnv* 06
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
IDT54/74FCT534
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
P20-1 17
D20-1 16
SO20-2
15
&
E20-1 14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
2603 cnv* 07
3 2
D
1
O
1
O
2
D
2
D
3
4
5
6
7
8
1
20 19
18
17
16
15
14
V
CC
O
7
OE
O
0
D
0
INDEX
D
7
D
6
O
6
O
5
D
5
L20-2
9 10 11 12 13
O
3
GND
CP
O
4
D
4
2603 cnv* 08
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
7.13
2
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
D
N
CP
O
N
Description
D flip-flop data inputs.
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
3-state outputs, (true).
3-state outputs, (inverted).
Active LOW 3-state Output Enable input.
2603 tbl 06
O
N
OE
FUNCTION TABLE
(1)
Inputs
Function
Hi-Z
Load Register
FCT534
Outputs
Internal
D
N
X
X
L
H
L
H
FCT374/574
Outputs
Internal
O
N
Z
Z
L
H
Z
Z
OE
H
H
L
L
H
H
CP
O
N
Z
Z
H
L
Z
Z
Q
N
NC
NC
L
H
L
H
Q
N
NC
NC
H
L
H
L
2603 tbl 05
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
u
u
u
u
L
H
u
Military
–0.5 to +7.0
Unit
V
Z = High Impedance
NC = No Change
= LOW-to-HIGH transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
(2)
Terminal Voltage
V
TERM
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to V
CC
with Respect to
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
120
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
–0.5 to V
CC
V
°C
°C
°C
W
mA
–55 to +125
–65 to +135
–65 to +150
0.5
120
NOTE:
2603 tbl 02
1. This parameter is measured at characterization but not tested.
NOTES:
2603 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability. No terminal voltage may
exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
7.13
3
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
OH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300
µ
A
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300
µ
A
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
2603 tbl 03
Unit
V
V
µ
A
µ
A
V
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.13
4
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
≥
V
HC
; V
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
Test Conditions
(1)
IN
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
≤
V
LC
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4.0
mA
—
2.2
6.0
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
4.0
7.8
(5)
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2603 tbl 04
7.13
5
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